GoldServe
Junior Member level 3

verilog bidirectional bus
Hi Guys,
I need some verilog coding help. I am trying to write a state machine that accomplishes what the logic trace below does.
USB Data Bus is a bi-directional port
USB Signals are command signals into the chip.
WR# and FRD# are read and write strobes into the chip
JTAG signals are standard JTAG signals out and TDO(IO35) is into the chip
If you look at the trace, you will see that at time t+3.2355hr, FRD# goes low and the bi-directional port changes direction right away and data is outputted onto the data bus. Any help in coding something like this would be helpful!
**broken link removed**
Hi Guys,
I need some verilog coding help. I am trying to write a state machine that accomplishes what the logic trace below does.
USB Data Bus is a bi-directional port
USB Signals are command signals into the chip.
WR# and FRD# are read and write strobes into the chip
JTAG signals are standard JTAG signals out and TDO(IO35) is into the chip
If you look at the trace, you will see that at time t+3.2355hr, FRD# goes low and the bi-directional port changes direction right away and data is outputted onto the data bus. Any help in coding something like this would be helpful!
**broken link removed**