need help for Via dropping method

[geekay]

Hai everyone,

i am using the intel proccessor .424 MM pitch Fbga this is the Different type of pin array's

can any one please suggess me how the via's put inside of the BGA and what is the Via Size?.

i here attached the intel Fbga foot print PIC.PDF

thanks
geekay.

 

[karesz]

Hi,
you see, if you do a Via into the pads, your PCB-producer must have a very good "planarizing" process-this isnt cheap & maybe is not simple to solder the chip over their...
I belief; its simpler & cheaper to apply between pads your (micro)Vias...
With 424 um pitch you can have (depend of your PCB producers process) a pyd diameter of i.e. 300um, ev. 250umeter with a hole of 75+/-25um...
Hole diameter is a question of process too, thenn the aspect of diameter/thickness is mosten at 10(ev. up to 15)!
You must discuss these details, in all cases, with your selected PCB producer!
K.

 

[geekay]

Hi Karesz,

in our pcb manufacture least dril szie is 8 mils.

in this case how can i put the micro via's in between the Bga pad's.

if u pit the via's on BGA pad's i cannot take the traces from inside of the BGA pin's. because the BGA pin pitch is very less (.419) 16.5 mils and the BGA pin to pin Air gap is 7.3 mils on we have ..

please give me some idea's to make the Via's or give me other solution.

 

[karesz]

Hali geekay,
you see, if your hole can be min. 8 mils=203umeter_also you have to forget this PCB producer/his technology for that design!
_or in all cases for the partielle production of FPGA part?
Do you have only ca. 95 um between pads?
Are you sure that the 0.419 pitch is not in inch to understand pls? It likes me some irrealistic with 95 um between pads & so much BGs on minimal distances...
What is the exact chip/package type pls?
Your only way is_ if pitch = 0.419 mm true is_to have between all landpattern an MICROVIA!!

Reason:
You cannot have cooper lines/wires between land pattern, also you must have so & so Multi Layer, means lot of (micro)vias!!
These means : cost, then they are to make with LASER drilling, i.e. 50 or 100 micron!!!
So an pitch needs it so a solution:-(.

Some Idea:
you have a relative normal ML-Board, but the TOP/BOT layers (under FPGA) areas a finest pitch Kapton/folie realised, and it is to laminate over the "basis PCB". Other side is the full PCB as finest print to produce_costs...
K.

 

[geekay]

Hi Karesz,

Thanks for the reply.

Now i am Reduced the Pad size 16 mils to 13 mils pad. so we have a 10.3 mils air gap between the Staggered pin's.

Now i can take the inner layer traces from the BGA inside pin's,but i need to put the via's(8 mils drill and 12 mils pad size) on pad.


if i put the Via's on pad what type of the problem i need to face ..

please see the footprint picture here:

https://i752.photobucket.com/albums/xx165/ganeshkumar06/intel04191MM_pitchStaggeredBGa.jpg
https://i752.photobucket.com/albums/xx165/ganeshkumar06/intel0424MM_pitchStaggeredBGa-1.jpg
please suggest me ...

thanks in advance
Geekay

 

[karesz]

Hi,
I think you should ask Intel_or a very competent firm for populating your FPGAs over solderability with your reduced pads!
Im not an expert in these subject...
For me is important question the reliability of soldered balls with reduced pad diameters!
With vias in pad: you will need a via-filling & GOOD planarization process for your PCB & these will be more expensive!...
I cannot see much on your footprint, but so as I checked is(for me) OK.
K.