Need help for solving error.

[rakeshkrr]

I am doing a project on micro UART using verilog.
I have all the files that are to be used for the project, but I have a problem with executing a .h extension file which is attached below along with other source codes for transmitter and receiver and baud rate.

Could any one can help me to execute this project?
Atleast is there any way to implement the contents of inc.h file into a new module which can be of .v extension file.

 

[devas]

Hi,

The inc.h file is a Verilog include file used in the Verilog files. I am not sure what you mean with "execute" but when you try to simulate the code you have to compile only the Verilog files (.v) and set the "include directory" option to the directory where the inc.h file is. For Modelsim the include directory option can be set in the GUI or on the vlog command line:
vlog <options> +incdir+<path> <file to compile>


Devas

 

[sudhirkv]

no need to change the extension of the file. u can use it in model sim and any of the synthesis tool. just add the file to the project.