Beardolphinaries
Member level 2
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Hi, I'am recently doing the inductor design on CMOS.
There is one thing I am confused. Usually, people do the patterned ground shield on polysilicon. In standard CMOS technology, the there is a thin gate oxide layer between the polysilicon and the p-substrate. Because I need model the CMOS technology file in ADS before the design, just don't know how to add these layers. I mean, the bottom layer is p-substrate, and on top of that, is that the gate oxide, poly, oxide,M1.... as usual? Or, for inductor design, this oxide thickness between the poly and p-sub can be any value?
Thanks a lot.
Hi, I'am recently doing the inductor design on CMOS.
There is one thing I am confused. Usually, people do the patterned ground shield on polysilicon. In standard CMOS technology, the there is a thin gate oxide layer between the polysilicon and the p-substrate. Because I need model the CMOS technology file in ADS before the design, just don't know how to add these layers. I mean, the bottom layer is p-substrate, and on top of that, is that the gate oxide, poly, oxide,M1.... as usual? Or, for inductor design, this oxide thickness between the poly and p-sub can be any value?
Thanks a lot.