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Need help: esign a clock gating circuit

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horzonbluz

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Need help: clock gating

I design a clock gating circuit now.
But it's my first time.
Could somebody help me? Give me some advice about it?
Thanks in advance. :(
 

flatulent

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need more data

We need more data.

1. What are the parameters of the clock (period, high time, low time, logic family)?

2. Can you generate the clock or does it come from an existing circuit?

3. What type of gating do you need (synchronous with the edges or not)?

4. Is the gating for a certain time or a certain number of clock cycles?
 

ted

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Also, maybe the clock gating is not the solution at all, depending what you want to do. For example, often having a "load enable" in a digital register is better than gating the clock. The "clock enable" is often a simple multiplexer which either loads the register with it's old contents or with the new value.

Be aware that gating a clock is always a bit tricky business, making easily glitches. You should draw the pulse diagrams, including circuit delays, and really see through all situations where one path may be faster than other (they usually are, and in a very unpredictable way: Be aware of component variations, load differences, temperature changes, and maybe even wind direction, monday mornings, plain bad luck and other more or less unknown factors)
 

RTL2GDSII

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Clock gating is used to reduce power consumption in ASIC.
Is there any document about this issue ?
 

simon2kk

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I understand that we can use "load enable" kind of control instead of clock gating.
I wonder if both techniques use the same power consumption.
Anyone has an experience on this?
 

horzonbluz

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:(
Hi, ted.
What's the "load enable"?
In my chip, the freq is about 300Mhz.
I have designed a clock gating circuit. But it can't satisfy the spec although it has no glitch. The method is: I use a D-flipflop to latch the enable signal and delay the system clock to generate the local clock sianal at the same time. Then use a Nand gate to generate the clock gating signal. The D-flipflop latch the enable signal on negtive going clock edges and output changes on the next positive clock edge.
 

ted

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The "load enable" is essentially a multiplexer which either offers the D input a new value or "recirculates" the old one. I have no direct measured power consumptiion figures in any physical implementation for that, but it obviously consumes more power than real clock gating, because the clock line load if nothing else. In a FPGA it is usually the easy and safe way of doing register control, while on a "real" ASIC it may be too power hungry.

I have seen some papers about the clock gating, one example is http://www.aiec.com/Publications/snug2000.pdf

I have only limited experience on hard ASICs, most of my work has been on FPGAs. And I have never implemented a clock gating circuitry on a chip. So, what I talk is much based on system level experiences.

Btw. Which specification is not satisfied with your design? I tried to figure out how your circuit works, but I did not like a couple of aspects on it: First, is the enable already synchronous with the clock, or do you risk metastability mess if it changes state exactly at/near the clock edge? Secondly, is the clock delay good enough, such thing tend to be unpredictable?

Ted
 

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