# need help-array vs vector

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#### fanwel

##### Full Member level 3
Dear all,

I have 4x4 matrix and I want to read this matrix row by row on each clock cycle. For example, row1 is read in cycle1, row2 is read in cycle2 and so on. I write the code using array but it cannot read the matrix row by row as I want.
Can anyone give me idea how to write this code, please? Many thanks

it depends. If you have an array of arrays, its going to be much easier:

Code:
type row_t is array(0 to 3) of std_logic_vector(7 downto 0);
type matrix_t is array(0 to 3) of row_t;

signal matrix   : matrix_t;
signal temp_row : row_t;
signal count    : unsigned(1 downto 0) := "00";

begin

process(clk)
begin
if rising_edge(clk) then
temp_row <= matrix( to_integer(count) );

count    <= count + 1;
end if;
end process;
If you're using a 2d, matrix type, things get a little more complicated as you have to use a function to extract the row, but it should generate the same logic.

Code:
type row_t is array(0 to 3) of std_logic_vector(7 downto 0);
type matrix_t is array(0 to 3, 0 to 3) of std_logic_vector(7 downto 0);;

signal matrix   : matrix_t;
signal temp_row : row_t;
signal count    : unsigned(1 downto 0) := "00";

function extract_row( m : matrix_t; row : integer) return row_t is
variable ret : row_t;
begin
for i in row_t'range loop
ret(i)  := m(row, i);
end loop;

return ret;
end function;

begin

process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( matrix, to_integer(count) );

count    <= count + 1;
end if;
end process;
NB: Matrix could be an input to your entity.

Dear TrickyDicky,

This is my code that I write referring to your code above:

library ieee;
use ieee.std_logic_1164.all;

entity TM is
port(input: in std_logic_vector (0 to 3);
clk: in std_logic);
end TM;

architecture arch of TM is
type row_t is array(0 to 3) of std_logic_vector(7 downto 0);
type matrix_t is array(0 to 3) of row_t;
signal matrix : matrix_t;
signal temp_row : row_t;
signal count : unsigned (1 downto 0) := "00";

begin
process(clk)

begin
if rising_edge(clk) then
temp_row <= matrix( to_integer(count) );
count <= count + 1;
end if;
end process;
end arch;

But, this error occurs:
Error (10482): VHDL error at TM.vhd(14): object "unsigned" is used but not declared.

add this line to the top of the code,

use ieee.numeric_std.all;

• fanwel

### fanwel

Points: 2
Dear vipinlal,

Thanks, its look okay now.

---------- Post added at 05:03 ---------- Previous post was at 04:30 ----------

Dear vipinlal,

By the way, can you explain the function of the line: use ieee.numeric_std.all;

---------- Post added at 05:38 ---------- Previous post was at 05:03 ----------

Dear all:

This is my testbench code:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity TM_tb is
end;

architecture bench of TM_tb is

component TM
port(input: in std_logic_vector (0 to 3);
clk: in std_logic);
end component;

signal input: std_logic_vector (0 to 3);
signal clk: std_logic;

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;

begin

uut: TM port map ( input => input,
clk => clk );

stimulus: process
begin
input <= "0100",
"0101",
"1110";
wait for 50ns;

stop_the_clock <= true;
wait;
end process;

clocking: process
begin
while not stop_the_clock loop
clk <= '1', '0' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;

When I compile this code in Quartus its okay. But then, when I compile it in ModelSim this error occurs:
**Error: H:/altera/TM5_test/TM_tb.vhd(30): Delay in signal assignment must be ascending.
Where I am wrong?Anyone help me please..

numeric_std is a library that contains the signed and unsigned types, and all the arithmetic functions that go along with them.

The error you are getting is because you're trying to assing 3 sequential inputs all at once without a delay beteen them. You probably want a delay between each one:

Code:
stimulus: process
begin
input <= "0100";
wait for 50 ns;
input <= "0101";
wait for 50 ns;
input <= "1110";
wait for 50ns;

• fanwel

Points: 2