Need guideline for NRZI output related question

[moonnightingale]

I need a guideline to start this verilog question. I have to write a verilog code that will output NRZI data stream.
Can u kindly explain me how to go about it.

 

[lostinxlation]

NRZI is the easiest one. If you show your attempt, we'll help.

 

[moonnightingale]

Kindly just give me broder guide line, how to start, actually i am studying verilog after two years.
I know all abt gate level, behaviour level but i am confused how to give input in verilog and how to go about clock
what i remember i use to give clock while using FPGA kit Spartan 3E by using it own clock of 25 MHZ crystal
how to generate clock in software code b/c in FPGA kit while making UCF file, i used to define the pin for clock and code use to pick clock from there

 

[tdminion]

In your 1st posting, you state, "...write a verilog code that will accept serial data and clock ...". Your (synthesizable) verilog module will simply list 'clock', "reset", and "serial_data_in" as inputs and "nrzi_data_out" as an output - same as the top level module that you have seen in your Xilinx ISE applications. There are a gazillion websites that explain how to put together a simple verilog module and write a simple verilog testbench to verify it. If I understand your question, you should not be concerned with where the clock, reset, din, and dout come from. You only need to be concerned about the logic to convert from NRZ to NRZI.

 

[moonnightingale]

In your 1st posting, you state, "...write a verilog code that will accept serial data and clock ...". Your (synthesizable) verilog module will simply list 'clock', "reset", and "serial_data_in" as inputs and "nrzi_data_out" as an output - same as the top level module that you have seen in your Xilinx ISE applications. There are a gazillion websites that explain how to put together a simple verilog module and write a simple verilog testbench to verify it. If I understand your question, you should not be concerned with where the clock, reset, din, and dout come from. You only need to be concerned about the logic to convert from NRZ to NRZI.

I have written this code, plz help me i am getting three errors
how we can use reset in this code

module nrziout(nrzi_data_out,clock,reset,serial_in);
output nrzi_data_out;
input clock,reset,serial_in;
reg nrzi_data_out;

initial
begin
clock=1'b0;
forever #10 clock=~clock;
end

//The NRZI has a transition at a clock boundry if bit being transmitted is logical 1
// and does not have transition if bit is 0

always @ (posedge clock)

begin
if (serial_in==1)
nrzi_data_out=~nrzi_data_out;
else
nrzi_data_out=nrzi_data_out;
end


endmodule

 

[tdminion]

I think you need to do some more studying/reading. These are very,very basic verilog questions that can be found on most websites. Typically you should have 2 modules, one module contains the design and the second module contains the testbench. The design module should be instantiated in the testbench module. Here is a link to a clear example: **broken link removed**

look at the 2 to 1 mux. Your clock generation and initial statement go in the testbench module. Also, you should include reset in the flip flop code.

 

[moonnightingale]

Ok i have written this code for single bit, is this code ok
How can i convert this input to a stream


module nrzi(out,in,clk);
output reg out;
input in,clk;
always @(posedge clk)
begin
if (in==0)
begin
out=out;
end
else
begin
out=~out;
end
end
endmodule

 

[tdminion]

In the link that I provided, the "32-bit Register" example shows how to reset your flip flop. Also look at the "32-bit Register Testbench," it shows how to instantiate your "nzri" module in the testbench. That's all you have to do.

 

[moonnightingale]

Plz i am stuck help me out,
kindly send me code and i will write test bench myself