need direct synthesis tools to map SystemC to Verilog

[yasser_shoukry]

systemc to verilog

Hi All,

I'm working now on modeling a small processor using the synthesiazable subset of SystemC.

However I do not have a clear flow after that. How can I synthesize this RTL base model. Is there direct synthesis tools or I have to use 3rd party tools to map SystemC into verilog for example

Regards,
Yasser

 

[yasser_shoukry]

Re: SystemC to Verilog

I chose systemC as it really decreases developing time with very powerful and easy to use verification.

I know that Synoposis has a tool called CoCentric Compiler that converts SystemC to HDL but I'm not sure of that