[need]DDR SDRAM controller code..............

[rakesh_aadhimoolam]

hi everyone........

i have gone through the links of opencores but thogh there is description of the project......

there exists no CVS files for the DDR SDRAM controller....

it would be grt if someone provides me the code...............or the link..........

thanks...........

 

[kib]

attached

 

[rakesh_aadhimoolam]

Thanks KIB............

it would be grt if you could do me one more favour..........

Any PDFs on DDR3 controller...........(Not the DAtasheets of Samsung or Micron or quimonda)

 

[kib]

I think datasheet should be a good starting point.
The main difference b/w DDR,DDR2,DDR3 is
DDR3's prefetch buffer width is 8 bit, whereas DDR2's is 4 bit, and DDR's is 2 bit
Theoretically, these modules could transfer data at the effective clockrate of 400-800 MHz (for a single clock bandwidth of 800-1600 MHz), compared to DDR2's current range of 200-533 MHz (400-1066 MHz) or DDR's range of 100-300 MHz (200-600 MHz).
Hence you should be able to start from your DDR controller and modify it to run for DDR3.