need circuit for the timing diagram

[rajakash]

hi,

when there is positive edge clock and change in input cause the output to one...

wat may be the circuit for this condition?????????

 

[emresel]

Is this helpfull?

entity my_design is
	Port( 	clk	: in std_logic;
			input : in std_logic;
			output : out std_logic);
end my_design;

architecture Behavioral of my_design is
signal input_old: std_logic;

begin
 process(clk)
  begin
		if(clk'event and clk='1') then
			if(input_old /= input) then
				output<='1';
			else 
				output<='0';
			end if;
		input_old <= input;
		end if;
 end process;
end Behavioral;

 

[yadavvlsi]

Please elaborate your question.?

 

[shelby]

emresels looks good. heres my take at a gate level ...
input in
output out
input clk

flop (.D(input), .Q(flop_out) .CLK(clk));
xor (.A(input), .B(flop_out) .Z(out));