Need advice on using Gate Oxide Capacitor

[Teddy]

gate oxide capacitor

Gentlemen,

I woul dlike to use gate oxide capacitor. I have P- substrate and would like to use PMOS device as a cap. How to bias it? Should N-well be connceted to the higher voltage than the gate or should I leave the the N-well float (e.g. it will be biased to gnd as substrate is).

Thank you for any educated advice!

 

[konqueror]

accumulation varactors

connect the source and drain togather.the two terminal will be the gate and source(drain).i think n well should be connected to higher potential

 

[rongli]

Gate Oxide Capacitor

I think the well should connect to substrate.the source& drain connetc together,the bias voltage will be in a range far away form operation.

 

[Hughes]

Gate Oxide Capacitor

Connect the Source, Drain, and Well together.

 

[mady79]

Re: Gate Oxide Capacitor

Biasing is critical for Gate Oxide cap .If you are using MOSCAP for a fixed value ,try to operate in accumulation or inversion region where the variations in cap value are minimal across VGST variations across corners.Use Varactor if you looking for some kind of tuning through cap.

 

[sisc1525]

Gate Oxide Capacitor

I think you can use two poly layers cap.or a poly-metal cap.their operation range is wider.

 

[Han]

Re: Gate Oxide Capacitor

One thing to notice.
In 0.18u and below,using thin oxide devices as capacitors (i.e connect the gate directly to VDD) is usually not recommended as it may cause reliability problems.
Just keep in mind

 

[Teddy]

Re: Gate Oxide Capacitor

Well , as I see the opinions vary...
I would like to use Gate Cap just because of area constraints. I never did before. I alwasy had luxury of MIM, Poly or trench caps before....

Another idea - does anyone hase experience with capacitance doublers? Schematic would for sure help!

 

[j2005]

Re: Gate Oxide Capacitor

Unfortunately, gate oxide capacitor is a poor relation of the poly, MIM etc.

You tie source, bulk and drain together. You'll have to make sure that the voltage across the gate - (source, drain, bulk) is maintained at more than Vth. Otherwise your capacitance will be unreliable. Don't use it if you need a steady capacitance over various corners and supply.

 

[drasta]

Re: Gate Oxide Capacitor

I think that you should connect source and drain together as one electrode and gate is the other and well must be connected (Nwell to a high potential).

 

[lakeoffire]

Gate Oxide Capacitor

I think gate oxide cap is of poor quality. Its linearity and temperature coefficiency is very bad. It is generally used as bypass cap or as compensation cap in opam, but is not recommended in signal path.

 

[okguy]

Re: Gate Oxide Capacitor

I have read once that such gate-oxide decoupling capacitor should not have too many contacts. Why?
Is there any technological reason???

 

[terryssw]

Re: Gate Oxide Capacitor

One thing to notice.
In 0.18u and below,using thin oxide devices as capacitors (i.e connect the gate directly to VDD) is usually not recommended as it may cause reliability problems.
Just keep in mind

Why? 0.18um digital devices always connected the thin oxide gate of MOSFET to digital signals (also have VDD potential) and they work wells in the digital circuits such as CPUs. I think if you follow the process rule, don't use the VDD supply larger than the technology limit, then you will not have problems (if you really have such problems, you can write a complain letter to your foundry)

 

[codec]

Re: Gate Oxide Capacitor

When Gate oxide capacitor is used, frequency dependence should be taken into account. In your case, NWC(Gate-to-NW/N+) might be better.

 

[Han]

Re: Gate Oxide Capacitor

One thing to notice.
In 0.18u and below,using thin oxide devices as capacitors (i.e connect the gate directly to VDD) is usually not recommended as it may cause reliability problems.
Just keep in mind

Why? 0.18um digital devices always connected the thin oxide gate of MOSFET to digital signals (also have VDD potential) and they work wells in the digital circuits such as CPUs. I think if you follow the process rule, don't use the VDD supply larger than the technology limit, then you will not have problems (if you really have such problems, you can write a complain letter to your foundry)

The problem is TDDB which cause reliability issues. Let's say avarage life time of mos is x years under some conditions. Statistically, about 1/2 of the time the voltage across the gate oxide will be VDD. The voltage across decap will alwayes be VDD so it's lifetime will be half of switched device (X/2). It becomes more critical in very thin oxide devices such as in 0.15u and below, but you should check about 0.18u.
Also ESD zaps and supply spike will not be filtered by channel resistance such as in digital inverter chain (there is always channel resistance in series with the gate right?) and will gradually degrade the oxide isolation.
One should take these into account when designing decaps.

 

[terryssw]

Re: Gate Oxide Capacitor

Isn't the decoupling cap also used in digital CPUs?

 

[alchen77]

Re: Gate Oxide Capacitor

When Gate oxide capacitor is used, frequency dependence should be taken into account. In your case, NWC(Gate-to-NW/N+) might be better.

I think you can use PMOS or NWC (like codec wrote) but you should always think about the other CMOS parasitic capacitance how to influence the circuit performance.

 

[omsi]

Gate Oxide Capacitor

hi,

if u look at the properties of mosfet as a capacitor ,the graph tells u that when mosfet's threshold voltage reaches we get bad cap.
so u bais mos either in saturation or accumulation but not in depletion region

 

[pbs681]

Re: Gate Oxide Capacitor

hi,

if u look at the properties of mosfet as a capacitor ,the graph tells u that when mosfet's threshold voltage reaches we get bad cap.
so u bais mos either in saturation or accumulation but not in depletion region

In theory we can get flat curve in the accumulation and inversion region. But in the real world, u only can get flat curve in inversion region. But if you use small L for the device, the capacitance in the inversion region too will decrease over the volatge.

U need to conect source, drain and bulk together. If you only connect source and drain together, u will get the overlap cap only, not the total cap.