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need a help to change verilog code to VHDL code...

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jian13389

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hi,

can someone pls convert this verilog code to vhdl code? i need it as fast as possible... thx...

this is the code:

// 8-bit by 8-bit Baugh-Wooley signed multiplier

module BWSM(x, y, p);

input [7:0] x, y;
output [15:0] p;

supply0 zero;
supply1 one;

wire [7:1]p1;
wire [7:1]p2;
wire [7:1]p3;
wire [7:1]p4;
wire [7:1]p5;
wire [7:1]p6;
wire [8:1]p7;
wire [9:1]p8;

wire [7:1]c1;
wire [7:1]c2;
wire [7:1]c3;
wire [7:1]c4;
wire [7:1]c5;
wire [7:1]c6;
wire [8:1]c7;
wire [9:1]c8;

// structural description of the multiplier circuit
assign p[0] = x[0]&y[0];
full_adder f1_1( x[1] & y[0], zero, x[0] & y[1], p1[1] , c1[1]); assign p[1]=p1[1];
full_adder f1_2( x[2] & y[0], zero, x[1] & y[1], p1[2], c1[2]);
full_adder f1_3( x[3] & y[0], zero, x[2] & y[1], p1[3], c1[3]);
full_adder f1_4( x[4] & y[0], zero, x[3] & y[1], p1[4], c1[4]);
full_adder f1_5( x[5] & y[0], zero, x[4] & y[1], p1[5], c1[5]);
full_adder f1_6( x[6] & y[0], zero, x[5] & y[1], p1[6], c1[6]);
full_adder f1_7( x[7] & ~y[0], zero, x[6] & y[1], p1[7], c1[7]);

full_adder f2_1( p1[2], c1[1], x[0] & y[2], p2[1] , c2[1] ); assign p[2]=p2[1];
full_adder f2_2( p1[3], c1[2], x[1] & y[2], p2[2] , c2[2] );
full_adder f2_3( p1[4], c1[3], x[2] & y[2], p2[3] , c2[3] );
full_adder f2_4( p1[5], c1[4], x[3] & y[2], p2[4] , c2[4] );
full_adder f2_5( p1[6], c1[5], x[4] & y[2], p2[5] , c2[5] );
full_adder f2_6( p1[7], c1[6], x[5] & y[2], p2[6] , c2[6] );
full_adder f2_7( x[7] & ~y[1], c1[7], x[6] & y[2], p2[7] , c2[7] );

full_adder f3_1( p2[2], c2[1], x[0] & y[3], p3[1] , c3[1] ); assign p[3]=p3[1];
full_adder f3_2( p2[3], c2[2], x[1] & y[3], p3[2] , c3[2] );
full_adder f3_3( p2[4], c2[3], x[2] & y[3], p3[3] , c3[3] );
full_adder f3_4( p2[5], c2[4], x[3] & y[3], p3[4] , c3[4] );
full_adder f3_5( p2[6], c2[5], x[4] & y[3], p3[5] , c3[5] );
full_adder f3_6( p2[7], c2[6], x[5] & y[3], p3[6] , c3[6] );
full_adder f3_7( x[7] & ~y[2], c2[7], x[6] & y[3], p3[7] , c3[7] );

full_adder f4_1( p3[2], c3[1], x[0] & y[4], p4[1] , c4[1] ); assign p[4]=p4[1];
full_adder f4_2( p3[3], c3[2], x[1] & y[4], p4[2] , c4[2] );
full_adder f4_3( p3[4], c3[3], x[2] & y[4], p4[3] , c4[3] );
full_adder f4_4( p3[5], c3[4], x[3] & y[4], p4[4] , c4[4] );
full_adder f4_5( p3[6], c3[5], x[4] & y[4], p4[5] , c4[5] );
full_adder f4_6( p3[7], c3[6], x[5] & y[4], p4[6] , c4[6] );
full_adder f4_7( x[7] & ~y[3], c3[7], x[6] & y[4], p4[7] , c4[7] );

full_adder f5_1( p4[2], c4[1], x[0] & y[5], p5[1] , c5[1] ); assign p[5]=p5[1];
full_adder f5_2( p4[3], c4[2], x[1] & y[5], p5[2] , c5[2] );
full_adder f5_3( p4[4], c4[3], x[2] & y[5], p5[3] , c5[3] );
full_adder f5_4( p4[5], c4[4], x[3] & y[5], p5[4] , c5[4] );
full_adder f5_5( p4[6], c4[5], x[4] & y[5], p5[5] , c5[5] );
full_adder f5_6( p4[7], c4[6], x[5] & y[5], p5[6] , c5[6] );
full_adder f5_7( x[7] & ~y[4], c4[7], x[6] & y[5], p5[7] , c5[7] );

full_adder f6_1( p5[2], c5[1], x[0] & y[6], p6[1] , c6[1] ); assign p[6]=p6[1];
full_adder f6_2( p5[3], c5[2], x[1] & y[6], p6[2] , c6[2] );
full_adder f6_3( p5[4], c5[3], x[2] & y[6], p6[3] , c6[3] );
full_adder f6_4( p5[5], c5[4], x[3] & y[6], p6[4] , c6[4] );
full_adder f6_5( p5[6], c5[5], x[4] & y[6], p6[5] , c6[5] );
full_adder f6_6( p5[7], c5[6], x[5] & y[6], p6[6] , c6[6] );
full_adder f6_7( x[7] & ~y[5], c5[7], x[6] & y[6], p6[7] , c6[7] );

full_adder f7_1( p6[2], c6[1], ~x[0] & y[7], p7[1] , c7[1] );
full_adder f7_2( p6[3], c6[2], ~x[1] & y[7], p7[2] , c7[2] );
full_adder f7_3( p6[4], c6[3], ~x[2] & y[7], p7[3] , c7[3] );
full_adder f7_4( p6[5], c6[4], ~x[3] & y[7], p7[4] , c7[4] );
full_adder f7_5( p6[6], c6[5], ~x[4] & y[7], p7[5] , c7[5] );
full_adder f7_6( p6[7], c6[6], ~x[5] & y[7], p7[6] , c7[6] );
full_adder f7_7( x[7] & ~y[6], c6[7], ~x[6] & y[7], p7[7] , c7[7] );
full_adder f7_8( ~x[7], ~y[7], x[7] & y[7], p7[8] , c7[8] );

full_adder f8_1( p7[1], x[7] , y[7] , p8[1] , c8[1] );
full_adder f8_2( p7[2], c7[1], c8[1], p8[2] , c8[2] );
full_adder f8_3( p7[3], c7[2], c8[2], p8[3] , c8[3] );
full_adder f8_4( p7[4], c7[3], c8[3], p8[4] , c8[4] );
full_adder f8_5( p7[5], c7[4], c8[4], p8[5] , c8[5] );
full_adder f8_6( p7[6], c7[5], c8[5], p8[6] , c8[6] );
full_adder f8_7( p7[7], c7[6], c8[6], p8[7] , c8[7] );
full_adder f8_8( p7[8], c7[7], c8[7], p8[8] , c8[8] );
full_adder f8_9( one , c7[8], c8[8], p8[9] , c8[9] );

assign p[7]=p8[1];
assign p[8]=p8[2];
assign p[9]=p8[3];
assign p[10]=p8[4];
assign p[11]=p8[5];
assign p[12]=p8[6];
assign p[13]=p8[7];
assign p[14]=p8[8];
assign p[15]=p8[9];

endmodule
 

assign statement in verilog is equivalent to writing the same thing in architecture body enclosed by begin and end.(however ,the word assign is to be removed )
and for instantiation use portmap....
this solves ur problem
 

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