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Necessary simulation check for PFD/CP?

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boshiouke

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pfd-cp mismatch

If my simulation includes only PFD, CP and the loop filter components, what simulations do I have to run to make sure my PFD/CP is working ok? I've run phase sweep between 2 identical frequencies going into the PFD, and plotted average integrated CP output current vs. phase difference to check to dead zone. Assuming the DC analysis for CP current mismatch over voltage variation and temp is already taken care of, what other simulations do I have to run for the combination of PFD/CP? Appreciate the comments!
 

rfsystem

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simulation check

You are nearly complete. In some PFD/CP combinations the input pulse width to the PFD need some minimum time. Also if the phase difference approaches the pulse width some nonlinearity could happen.That is no issue because it is not an locking point.

Phase noise or jitter is needed for phase noise calculation. Also timing jitter because of VDD noise is a further pracical issue.
 

    boshiouke

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Thanks, rfsystem. I've read quite a bit of your postings on PLL/dead zone, and they're quite helpful.

Let me make sure I understand. So basically once the dead zone issue is taken care of by sweeping input phase difference, the simulation for PFD/CP is pretty much done. Is that correct? Well, of course, I also need to simulate the phase noice from PFD/CP.
 

rfsystem

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Yes, the reason why linearity is important today is because the sigma-delta modulation makes phase pertubations. The noise fequency shaping shift the noise in the range where it is filtered by the analog loop filter. The nonlinearity violate the frequency shaping effect. The noise comes up in the frequency range where the loop gain and the analog filter does not help.
 

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Thanks again for the reply. I do have a question about the plot of CP current vs. phase difference. Is the curve supposed to be symmetrical against both x and y axis? If not, what does that say about the design? Besides, when the phase difference is zero, is the average integrated CP current supposed to be zero? My impression was, to prevent VCO from drifting, CP has to produce certain amount of current even when it's locked, i.e no phase difference. If that's the case, then the average integrated CP current should NOT be zero then. Is that right?
 

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In most cases you can not avoid a small unsymmetric behaviour. That is because the UP od DOWN current is not equal or the dynamic matching is not perfect. Try to make both static and dynamic matching. If both matching are not perfect the resulting reference spur is higher. You can make a FFT of the current in the locked condition (zero charge), calculate trough your analog filter, converting into phase domain (1/s) in the VCO and you get the reference spur.

The number of specs for the chargepump and detector depend on the system usage. Ask the guy who give you the order.
 

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Thanks again for the reply. My question is, isn't it true that you actually NEED to have certain amount of current pulse at charge pump output @ zero phase difference for the PLL to work? If the answer is yes, then doesn't that mean that in the CP current vs. ΔΦ plot the curve should NOT cross the (0,0) point? Thank you.
 

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The effect is little different. The phase/frequency detector provide a minimum pulse width for one of the ouput pulses if the phase difference is nonzero. So either the up or the down current goes to minimum pulse length. If the phase difference is zero both pulses are active. What goes trough zero is the sum of the positive up and the negative down current. Btw at zero phase the pulse width is not equal to the minimum pulse with but a little longer. That is because the logic gate which make the reset pulse within the phase/frequency detector have a NAND. This is little slower of both edges rise at the same time instead one is already high. You can model that by

TUP=TMIN+TMD*(t/TMD+sqrt((t/TMD).^2+1))

where TMIN is the minimum pulse width and TMD is the delay difference of the NAND between both switching and only one input switching.
 

    boshiouke

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boshiouke

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Got it! Thanks a lot.

Btw, once a PFD/CP works @ 30Mhz Fref, for it to work @ much lower frequency, say, 30KHz, the width of the reset pulse should be made wider accordingly, correct? But, what's the implication of a longer reset pulse? Is there a rule of thumb for a proper reset pulse width?(if you happen to know the publication that talks about this) I suppose the lower bound is to avoid dead zone, correct? What's the upper bound then? Thanks and really appreciate it!
 

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Sorry I did not found any useful material. I try for myself to model the effects. It is much quicker than to google around. So model the charge-pump current as switch controlled current source with some rise and fall time. To make it easier to start with equal rise and fall but different for up and down. Then make the equations.

The settling is described by single pole. So you get IUP=IUP0*(1-exp(t/TRFUP))

If the minimum pulse does not lead to complete settling of the current the gain will be reduced at zero phase.

So the TMIN should be a factor higher than TRFUP. Some where between 2-5 is ok. I have read that somewhere, sometimes.

It is easier for me to remind the math.
 

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Thanks again.

I'm just wondering, if a PFD/CP works fine w/o dead zone @ 30MHz, is there any reason that it might not work or run into dead zone issue @ 30KHz? Besides, I'm not sure if I got the answer to my previous question, which is "the upper bound for the reset delay"? Thanks a bunch!
 

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The upper bound is defined by the current noise. If the chargepump is active it inject noise into the loop filter. Also reference ripple is little bit higher. So the trade is between linearity and noise contribution.

At 30kHz there is no need to change anything. Noise contribution is less. But filter is slower. That trade depend on yout hole loop architecture.
 

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Thanks once again for the input.

In Wolaver's PLL book p.63, he mentioned PFD in high frequency operation, in which he talked about maximum useful frequency for a PFD, minimum duration of State 2 for a tristate PFD and maximum phase within the linear range. My question is, for a PFD to be considered "working", does its linear range have to cover the entire 360 degree @ PFD's highest Fref? cuz it seems to me that PFD will always have a NONZERO duration in State 2, which results that linear range can not cover the entire 360 degree. Is that correct? The problem is, when I run the PFD at different frequency, it does seem to cover the entire 360 if running below certain frequency, beyond which it won't.

Appreciate your input.
 

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The operating phase range is limited by the minimum reset time and some small additional delay. So at higher frequencies the phase range in radians is smaller than 2*pi. The effect on the PLL circuit is that the settling time is smaller as long as the PLL stays within the phase range. So it does not wrap. It the PLL wrpas the settling is longer.

Linearity is no issue at higher phase difference. It is only important around the locking point.
 

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