Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ncverilog warning issue

Status
Not open for further replies.

leeguoxian

Member level 3
Joined
Jun 20, 2006
Messages
66
Helped
6
Reputation
12
Reaction score
2
Trophy points
1,288
Activity points
1,778
scheduled event for delayed signal

Dear all :

I'm running ncverilog with sdf annotated . Than the following message came up :

Scheduled event for delayed signal of net "D" at time xxxx PS was canceld
File: xxx/xxx/xxx/std.v , line = 8569 ;
Scope test.u0.xxx.xxxx
Time : xxxx PS

What does it meas ?? Is there anything wrong with the std cell behavior model ??

Following is the definition of the DFF cell :

module DFFPETX1 (Q, QN, D, CK, E, RN);
output Q, QN;
input D, CK, E, RN;
reg NOSIFIER;
supply1 xSN;
supply1 dSN;
buf XX1 (xRN, RN);

udp_edfft I0 (n0, D, CK, xRN, xSN, E, NOSIFIER);
buf I1 (Q, n0);
not I2 (QN, n0);
and I3 (Deff, xRN, D);
and I4 (Dcheck,E,xRN);
and I5 (check,E, D);
specify
specparam
tplh$CK$Q = 1.0,
tphl$CK$Q = 1.0,
tplh$CK$QN = 1.0,
tphl$CK$QN = 1.0,
tsetup$D$CK = 1.0,
thold$D$CK = 0.5,
tsetup$CK$CK = 1.0,
thold$CK$CK = 0.5,
tsetup$E$CK = 1.0,
thold$E$CK = 0.5,
tsetup$RN$CK = 1.0,
thold$RN$CK = 0.5,
tminpwl$CK = 1.0,
tminpwh$CK = 1.0,
tperiod$CK = 1.0;
// path delays
(posedge CK *> (Q +: Deff)) = (tplh$CK$Q, tphl$CK$Q);
(posedge CK *> (QN -: Deff)) = (tplh$CK$QN, tphl$CK$QN);
// timing checks
$setuphold(posedge CK &&& (Dcheck == 1), posedge D, tsetup$D$CK, thold$D$CK, NOSIFIER);
$setuphold(posedge CK &&& (Dcheck == 1), negedge D, tsetup$D$CK, thold$D$CK, NOSIFIER);
$setuphold(posedge CK, posedge E &&& (RN == 1), tsetup$E$CK, thold$E$CK, NOSIFIER);
$setuphold(posedge CK, negedge E &&& (RN == 1), tsetup$E$CK, thold$E$CK, NOSIFIER);
$setuphold(posedge CK, posedge RN, tsetup$RN$CK, thold$RN$CK, NOSIFIER);
$setuphold(posedge CK, negedge RN, tsetup$RN$CK, thold$RN$CK, NOSIFIER);
$width(negedge CK, tminpwl$CK, 0, NOSIFIER);
$width(posedge CK, tminpwh$CK, 0, NOSIFIER);
$period(posedge CK, tperiod$CK, NOSIFIER);
endspecify
endmodule
 

scheduled event for delayed signal of net

it seems a sdf syntax problem!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top