NCverilog --- Unbound instance

[lebron1]

Hi all, I don't care signals of analog modules which instantiated in chip top level . But if i don't define analog modules in .v file , ncverilog will show "Unbound instance" and show error to stop simulation. Is there any command to allow instantiate instances but not define them in .v, just like a blackbox. Thanks.

 

[skyfaye]

I'm pretty sure you must define all the modules instantiated. You can just make a dummy module that only has the I/O pins.

- Hung