Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

NCverilog --- Unbound instance

Status
Not open for further replies.

lebron1

Newbie level 2
Joined
May 21, 2009
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,291
Hi all, I don't care signals of analog modules which instantiated in chip top level . But if i don't define analog modules in .v file , ncverilog will show "Unbound instance" and show error to stop simulation. Is there any command to allow instantiate instances but not define them in .v, just like a blackbox. Thanks.
 

skyfaye

Member level 5
Joined
Feb 25, 2008
Messages
82
Helped
25
Reputation
50
Reaction score
11
Trophy points
1,288
Activity points
1,876
I'm pretty sure you must define all the modules instantiated. You can just make a dummy module that only has the I/O pins.

- Hung
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top