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Ncverilog + SDF back-annotation: Analysis Coverage

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kalar

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Hi,

I manage to run gate-level simulation of my post-routed netlist with ncverilog, and i can observe the increased delay of all cells and nets at simvision. My only question is about the sdf statistics that ncverilog reports, as I would excepted 100% annotation but it reports only 2.67% for paths and 2.58% for tchecks.

About the design and the procedure: top.v is the post-routed netlist, tb.v is the benchmark where top.v is instantiated. Inside the top.v, the technology lib is included (lib.v). At tb.v, this is included too $sdf_annotate("./top_v3.sdf", my_testbench.add_top);. Sdf was created in Encounter.

I run ncverilog as follows:
Code:
ncverilog ./top.v \
          ./tb/tb.v \
          +maxdelays \
          +access+rw > log

Report of running ncverilog:
Code:
    Reading SDF file from location "./top_v3.sdf"
    Annotating SDF timing data:
        Compiled SDF file:     top_v3.sdf.X
        Log file:              
        Backannotation scope:  my_testbench.add_top
        Configuration file:    
        MTM control:           
        Scale factors:         
        Scale type:            
    Annotation completed successfully...
    SDF statistics: No. of Pathdelays = 11056  [B]Annotated = 2.67%[/B] -- 
                    No. of Tchecks = 15478  [B]Annotated = 2.58%[/B] 
                        Total        Annotated      Percentage
         [B]Path Delays[/B]           11056             295            2.67
               $hold             383               0            0.00
              $width            5872             200            3.41
           $recovery             383               0            0.00
          $setuphold            8840             200            2.26

So my question is why the Annotated percentage is only abou 2 % and not 100%? At simvision I can see all the cells and nets to be annotated. In addition, what Path Delays represents (for sure not all the paths of my design, as it is a very small design)?

My best,
Harry
 

Hi,

I manage to run gate-level simulation of my post-routed netlist with ncverilog, and i can observe the increased delay of all cells and nets at simvision. My only question is about the sdf statistics that ncverilog reports, as I would excepted 100% annotation but it reports only 2.67% for paths and 2.58% for tchecks.

About the design and the procedure: top.v is the post-routed netlist, tb.v is the benchmark where top.v is instantiated. Inside the top.v, the technology lib is included (lib.v). At tb.v, this is included too $sdf_annotate("./top_v3.sdf", my_testbench.add_top);. Sdf was created in Encounter.

I run ncverilog as follows:
Code:
ncverilog ./top.v \
          ./tb/tb.v \
          +maxdelays \
          +access+rw > log

Report of running ncverilog:
Code:
    Reading SDF file from location "./top_v3.sdf"
    Annotating SDF timing data:
        Compiled SDF file:     top_v3.sdf.X
        Log file:              
        Backannotation scope:  my_testbench.add_top
        Configuration file:    
        MTM control:           
        Scale factors:         
        Scale type:            
    Annotation completed successfully...
    SDF statistics: No. of Pathdelays = 11056  [B]Annotated = 2.67%[/B] -- 
                    No. of Tchecks = 15478  [B]Annotated = 2.58%[/B] 
                        Total        Annotated      Percentage
         [B]Path Delays[/B]           11056             295            2.67
               $hold             383               0            0.00
              $width            5872             200            3.41
           $recovery             383               0            0.00
          $setuphold            8840             200            2.26

So my question is why the Annotated percentage is only abou 2 % and not 100%? At simvision I can see all the cells and nets to be annotated. In addition, what Path Delays represents (for sure not all the paths of my design, as it is a very small design)?

My best,
Harry

I would start by reviewing the SDF and the scopes, maybe your tb doesn't match your SDF. this is a pretty common mistake.
then review the netlist, make sure it is the postrouted one
then review the SDF to make sure it is also generated for the postrouted design
 

After some working around that I noticed the followings.

The lib.v, which contains all the functional verilog modules for all cells in the library, I had included it at my top.v file (post-routed netlist) in order to find the cells modules. Therefore when I run ncverilog command this creates all INCA libs with all the cells. However, my sdf file contain only a few cells that there are in my top.v (without the lib.v). Thus I was getting a very low annotation percentage (top_cells/all_lib_cells = low %).

So, by using the same same INCA libs, I deleted the include lib.v from top.v and I re-ran the ncverilog command. The modules of cells are found at INCA libs which i created earlier, so no problem was reported. Finally I got 100% annotation as now only the cells from my top.v was read from INCA libs and matched to my sdf, instead of trying to match all the cells from lib.v to my sdf.

Code:
   SDF statistics: No. of Pathdelays = 295  [B]Annotated = 100.00%[/B] -- 
                   No. of Tchecks = 400  [B]Annotated = 100.00%[/B] 
                        Total        Annotated      Percentage
         Path Delays             295             295          100.00
              $width             200             200          100.00
          $setuphold             200             200          100.00
    Building instance overlay tables: .................... Done

To summarize:

====Step 1====
I ran
Code:
ncverilog lib.v
to create the INCA_libs of all cells in my technology library.

====Step 2====
Then I ran
Code:
ncverilog ./top.v \
          ./tb/tb.v \
          +maxdelays \
          +access+rw > log
without including the lib.v to my top.v or tb.v. This command is successful, as it reads all the cells from INCA_libs that I created in the first step and also gives me 100% annotation.

It works fine this approach but I need 2 steps to run full back-annotation. Do you know If I can do it in one step (one command)?

My best,
Harry
 

interesting issue and solution.

I guess you could have generated a flat netlist that would include lib.v modules into top.v, and only the meaningful sections of lib.v would be included.
 

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