[NCVerilog] how to include multiple files to be compiled?

[joder]

Hi,
I'd like to include many design files into compilation with some library files.
Could anyone show me a quick example in its command line?
I wanna to integrate the simulation into Makefile. Any example is much appreciated.

Thx a lot.

 

[joder]

To be more precise, I need to use multiple-steps in NC (ie. using ncvlog, ncelab and ncsim) to do the simulation.
In ncverilog, i can use -f design_filelist and -v library files to simulate. But I don't know how do use multiple steps in NC.
Thx.