sevid
Member level 2
cuvmur
Dear all :
when i simulate my codes with NC-Verilog after synthesizing them with DC,some reference errors appear,the errors is list as follow:
ncelab: *E,CUVMUR: instance of module/UDP 'fdesf1a3' is unresolved
in 'worklib.ar:module'.
ncelab: *E,CUVMUR: instance of module/UDP 'clk1a3' is unresolved
in 'worklib.ar:module'.
......
ncelab: *W,CUVWSP (.\simplecpu.v,221|26): 1 port was not connected:
CO
ncelab: *E,CUVMUR: instance of module/UDP 'clk1b6' is unresolved
in 'worklib.dr:module'.
ncelab: *F,MAXERR: maximum error count reached (15).
and in my top file, i have used the system task $sdf_annotate as:
initial
begin
$sdf_annotate("design.sdf",mydesign, ,"design.log");
end
Thanks in advance!
Dear all :
when i simulate my codes with NC-Verilog after synthesizing them with DC,some reference errors appear,the errors is list as follow:
ncelab: *E,CUVMUR: instance of module/UDP 'fdesf1a3' is unresolved
in 'worklib.ar:module'.
ncelab: *E,CUVMUR: instance of module/UDP 'clk1a3' is unresolved
in 'worklib.ar:module'.
......
ncelab: *W,CUVWSP (.\simplecpu.v,221|26): 1 port was not connected:
CO
ncelab: *E,CUVMUR: instance of module/UDP 'clk1b6' is unresolved
in 'worklib.dr:module'.
ncelab: *F,MAXERR: maximum error count reached (15).
and in my top file, i have used the system task $sdf_annotate as:
initial
begin
$sdf_annotate("design.sdf",mydesign, ,"design.log");
end
Thanks in advance!