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NC-Verilog post-simulation problem

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sevid

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cuvmur

Dear all :

when i simulate my codes with NC-Verilog after synthesizing them with DC,some reference errors appear,the errors is list as follow:

ncelab: *E,CUVMUR: instance of module/UDP 'fdesf1a3' is unresolved
in 'worklib.ar:module'.
ncelab: *E,CUVMUR: instance of module/UDP 'clk1a3' is unresolved
in 'worklib.ar:module'.
......
ncelab: *W,CUVWSP (.\simplecpu.v,221|26): 1 port was not connected:
CO
ncelab: *E,CUVMUR: instance of module/UDP 'clk1b6' is unresolved
in 'worklib.dr:module'.
ncelab: *F,MAXERR: maximum error count reached (15).

and in my top file, i have used the system task $sdf_annotate as:
initial
begin
$sdf_annotate("design.sdf",mydesign, ,"design.log");
end

Thanks in advance!
 

Shurik

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ncelab: *e,cuvmur

Hi!!
Try
nchelp ncelab CUVMUR
 

tukken

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*e,cuvmur

check if you include your library path
 

stormwolf

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cuvwsp

I think the major reason is the library.
 

love2read

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ncelab: *e,cuvmur: instance

check your library link
 

sevid

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ncelab cuvmur

Thanks for all of you.
But this is my first post-sim with NC-Verilog, pls tell me how to link or include my library.
Thanks in advance!

sevid
 

xuanzhu

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ncelab: *e,cuvmur:

if you do the post simulation
you need include your library file in your gate netlist or use a file to list the library file, testbench file and gate netlist. The library file includes all the gate discreption that you refer in your netlist
for example
`include "mylib.v"
module xxx
.....
endmodule
or a list file whose content is like the following
mylib.v
tb_xxx.v
xxx.v
 

sevid

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e,cuvmur

To xuanzhu :

but my library file is a **.db file when i synthesize my design with DC.
you mean that i should switch it to a **.v file,yes or no?but how?

thanks a lot.
sevid

Added after 1 hours 47 minutes:


INCLUDE /path/to/ur/library/file //added in my cds.lib
when i specify my **.db in this way,i get the same error.
it seems like i must translate my **.db into **.lib,or cds.lib?but how?

I really appreciate ur help .
sevid
 

cfriend

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include library in verilog

In my opinion, you can get *.v file from the lib dir. for simulation.
 

xuanzhu

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ncelab: *w,cuvwsp

to sevid
this verilog library file is provided by your vender, such as tsmc, smic, or umc, etc. It is neither written by you, nor converted by your library db file
 

sevid

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ncverilog nowarn

To all :
What i am doing now is just an experiment,and i only have a **.db library file.
But from someone,i have heard that you can get ur library for post-sim with the help of "library analyzer" which is embedded in VSS,or with the "library compiler" which is embedded in DC.
but i don't know how to get it ,help!

Thanks a lot.
sevid
 

sevid

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ncelab verilog module search order

We can only convert our .lib library files to .db,.hdl,.edif library files with the help of library compiler.
So i cann't translate my .db library file to .v file with it.
Thanks to all of you.
The end of this topic.

sevid
 

Markchang

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ncelab udp

I think that you should be add below option
ncelab -access rwc -nowarn CUVWSP
 

sumit_techkgp

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xxx sevid xxx

Please include library udp in your simulator file list
Sumit
 

bossbebes

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nc verilog library compiler

And what about the scope in the sdf file.

Do you know what should be this field ?
What does it means?

Thxs

A beginner ....
 

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