Sep 5, 2021 #1 S sivamani Full Member level 6 Joined Jan 30, 2007 Messages 336 Helped 46 Reputation 92 Reaction score 43 Trophy points 1,318 Location Hyderabad Activity points 2,919 RTL Designer jobs@narendraJobs JD for req1: RTL Design Experience : 5 to 15 yrs Notice : Immediate to 30 days only Positions : 10 WFH : Available till pandemic gets over Skills Required: 5 to 10 yrs years of Design development experience. Should have Good know-how of Verilog and have good RTL coding skills Should have Good understanding of Digital Design Flow (Clock domain crossing (CDC), Lint) , Spyglass Tools Should have Good debugging skills Should have Good communication, interpersonal and teamwork skills. Processor Design (specially ARM based) is an added advantage . JD for req 2: RTL Design Experience : 5 to 15 yrs Notice : Immediate to 30 days only Positions : 10 WFH : Available till pandemic gets over Skills Required: Responsible for IP / sub-system level micro-architecture development and RTL coding. Prepare block/sub-system level timing constraints. Integrate IP/sub-system. Perform basic verification either in IP Verification environment Experience in Logic design / micro-architecture / RTL coding is a must. Expertise in Verilog/VHDL is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB. Experience in Synthesis / Understanding of timing concepts for ASIC Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Apply belowhttps://forms.gle/jFmy9jfg8LwxfPKr7 Thanks NarendraJobs
RTL Designer jobs@narendraJobs JD for req1: RTL Design Experience : 5 to 15 yrs Notice : Immediate to 30 days only Positions : 10 WFH : Available till pandemic gets over Skills Required: 5 to 10 yrs years of Design development experience. Should have Good know-how of Verilog and have good RTL coding skills Should have Good understanding of Digital Design Flow (Clock domain crossing (CDC), Lint) , Spyglass Tools Should have Good debugging skills Should have Good communication, interpersonal and teamwork skills. Processor Design (specially ARM based) is an added advantage . JD for req 2: RTL Design Experience : 5 to 15 yrs Notice : Immediate to 30 days only Positions : 10 WFH : Available till pandemic gets over Skills Required: Responsible for IP / sub-system level micro-architecture development and RTL coding. Prepare block/sub-system level timing constraints. Integrate IP/sub-system. Perform basic verification either in IP Verification environment Experience in Logic design / micro-architecture / RTL coding is a must. Expertise in Verilog/VHDL is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB. Experience in Synthesis / Understanding of timing concepts for ASIC Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Apply belowhttps://forms.gle/jFmy9jfg8LwxfPKr7 Thanks NarendraJobs