N25Q256A Flash configuration

[trungnd33]

Hi guys,

I have a device which read from N25Q256A (Digilent Pmod SF3) via SPI. My device sends 16 bit address addr[15:0] to the flash SPI along with the read command 03, expecting the flash chip will return 4 byte of data starting at address {addr[15:2], 2'b00} of the flash chip.
Given, I cannot make any modification to my device, how can I configure the flash chip so that it will always ignore the 2 LSB of address and return 4 bytes of data I expected?
In case, you know other flash allow that configuration, please recommend.

Much appriciated

 

[KlausST]

Hi,

I cannot make any modification to my device,

Without any modifications ... nothing will change.

So you need to modificate something.
What modifications are allowed?
* software modification?
* hardware modification of the datastream of MOSI?
* hardware modification in the meaning of desoldering one flash chip and replacing it with a different chip?
* you speak about "configuration". So - if I understand correctly - you want a 4 byte (32bit) memory organisation. This chip does not provide something like this.
And even if there exist a x32 bits organized chip, I never heard of ignoring the LSBs of the addressing.
(They rather make the MSB unused)

Klaus

 

[trungnd33]

Hi,


Without any modifications ... nothing will change.

So you need to modificate something.
What modifications are allowed?
* software modification?
* hardware modification of the datastream of MOSI?
* hardware modification in the meaning of desoldering one flash chip and replacing it with a different chip?
* you speak about "configuration". So - if I understand correctly - you want a 4 byte (32bit) memory organisation. This chip does not provide something like this.
And even if there exist a x32 bits organized chip, I never heard of ignoring the LSBs of the addressing.
(They rather make the MSB unused)

Klaus

Sorry for any confusion. No modifications to the reader. Any modification on flashchip’s side is allowed.
What I meant was:
When mosi sends address either 0x1001, 0x1002 or 0x1003, for example, the flash miso always returns data in address 1000, 1001, 1002 and 1003 just as if mosi sends 1000. Thanks

 

[trungnd33]

Sorry for any confusion. No modifications to the reader. Any modification on flashchip’s side is allowed.
What I meant was:

First, the flash miso always returns data of 4 bytes when received a read command.

When mosi sends address either 0x1001, 0x1002 or 0x1003, for example, the flash miso always returns data in address 1000, 1001, 1002 and 1003 just as if mosi sends 1000.

 

[trungnd33]

Hi,


Without any modifications ... nothing will change.

So you need to modificate something.
What modifications are allowed?
* software modification?
* hardware modification of the datastream of MOSI?
* hardware modification in the meaning of desoldering one flash chip and replacing it with a different chip?
* you speak about "configuration". So - if I understand correctly - you want a 4 byte (32bit) memory organisation. This chip does not provide something like this.
And even if there exist a x32 bits organized chip, I never heard of ignoring the LSBs of the addressing.
(They rather make the MSB unused)

Klaus

Hi,


Without any modifications ... nothing will change.

So you need to modificate something.
What modifications are allowed?
* software modification?
* hardware modification of the datastream of MOSI?
* hardware modification in the meaning of desoldering one flash chip and replacing it with a different chip?
* you speak about "configuration". So - if I understand correctly - you want a 4 byte (32bit) memory organisation. This chip does not provide something like this.
And even if there exist a x32 bits organized chip, I never heard of ignoring the LSBs of the addressing.
(They rather make the MSB unused)

Klaus

I hope this will explain well enough

 

[KlausST]

Hi,

Why not answering my questions?

I don't know what "your device" is, nor what "the reader" is, nor what exactly to the "flashchip's side" belongs.
Draw a sketch if you want useful feedback.

Klaus

 

[trungnd33]

Hi,

Why not answering my questions?

I don't know what "your device" is, nor what "the reader" is, nor what exactly to the "flashchip's side" belongs.
Draw a sketch if you want useful feedback.

Klaus

My device and the reader are the same and have SPI interface as described, cannot tell you more about it. Any other thing can be changed.
------------- ------------
| my device| ---SPI---> | flash chip|
------------- ------------

 

[KlausST]

Hi,

Then good luck with your project.

Klaus

 

[FvM]

In general terms, you want to patch the command sequence sent to the SPI flash, for some arbitrary reason. This can be probably done with a CPLD or even discrete logic. The patched data in bit sequence need to stay within the original clock frame, can be demanding depending on the clock frequency which wasn't yet mentioned. It's also important to know if the flash is using 4-bit mode in the data phase which turns data into a bidirectional signal.