Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

n bit decoder binary to 7seg

Status
Not open for further replies.

amin5659

Member level 3
Joined
Mar 28, 2015
Messages
55
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
522
hi all.
i want to design a n bit decoder binary to 7 segment.
the problem that i faced is that i cant find the number of output lines.....
i mean for n=4 the the max number is 15 that need 7*2 output lines
and n=5,6 too.
but for n=7 the max number is 127 that have 3 number also needs 7*3 output line and....It continues to grow with a pattern.but i cant find out a formula for that....
please help me..
regards.
 

i didnt under stand that.
log(10)=1 isnt it?
so the formula become to ceil(n*log(2))????
and what is ceil??????!
 

oh.you are right.about ceil i apologies honestly i knew that with different name because my english isnt well.
and about the formula if we add 1 thats be correct.
really thanks.you was very help full.
 

and about the formula if we add 1 thats be correct
No, you don't add 1. Just use the smallest following integer...

E.g. 7*log(2) = 2.1
Number of digits = ceil(2.1) = 3
 
yes i was mistake that with floor.
thanks alot.
 

another question.i define n as integer.
when i want to define output like this:
o:eek:ut std_logic_vector (ceil(n*(log(real(2)))-real(1)) downto 0)
i receive this:* can not have such operands in this context.
==========
and when i change than to this:
o:eek:ut std_logic_vector (ceil(real(n)*real(log(real(2)))-real(1)) downto 0)
i receive this:Range declaration does not match type definition.
======
can you help me??

- - - Updated - - -

i am waiting for answer.....
 

another question.
when i want to define entity like this:entity ex2 is
generic(n:integer:=13);
port(
i:in std_logic_vector (n-1 downto 0);
o:eek:ut std_logic_vector (n*(log(real(2)))-real(1) downto 0)
);
end ex2;
i receive this:* can not have such operands in this context.
and when i change output to this:eek::eek:ut std_logic_vector (real(n)*(log(real(2)))-real(1) downto 0)
i receive this:Range declaration does not match type definition.
how can i define output for this correct.please help me.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top