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my TEXTIO problem,please help me

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rodgurt

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Hi,
I am newbie in VHDL...I am doing a project in image processing. After I finished my design, I want to create testbench with textio.
I learn TEXTIO from a book published by NEWNESS. For the first time I try to modify their code to read my own file. But unfortunately, I fail. I have asked my friend but he cant answer it too. So please help me. What is wrong part of my code? I Can not read my file. Thank you.
Here it is :
------------------------------------------------------------------
-- Test bench for Circuit1
------------------------------------------------------------------
------------------------------------------------------------------
-- Libraries and packages to use
------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;

LIBRARY STD;
USE std.textio.ALL;


------------------------------------------------------------------
-- Test bench Entity
------------------------------------------------------------------
ENTITY compress_decompress_top_tb IS
END compress_decompress_top_tb;
ARCHITECTURE Behavioural OF compress_decompress_top_tb IS
------------------------------------------------------
-- Component Declaration for the Unit Under Test (UUT)
------------------------------------------------------
COMPONENT compress_decompress_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
ENA : IN std_logic;
cmode : IN std_logic_vector(6 downto 0);
xin : IN std_logic_vector(7 downto 0);
xout : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
------------------------------------------------------
-- Inputs
------------------------------------------------------
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '1';
SIGNAL ENA : STD_LOGIC := '0';
SIGNAL cmode : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
SIGNAL xin : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
------------------------------------------------------
-- Outputs
------------------------------------------------------
SIGNAL xout : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
------------------------------------------------------
-- integer to bit_vector conversion
function int2bit_vec(A: integer; SIZE: integer) return BIT_VECTOR is
variable RESULT: BIT_VECTOR(SIZE-1 downto 0);
variable TMP: integer;
begin
TMP:=A;
for i in 0 to SIZE-1 loop
if TMP mod 2 = 1 then RESULT(i):='1';
else RESULT(i):='0';
end if;
TMP:=TMP / 2;
end loop;
return RESULT;
end;


BEGIN
------------------------------------------------------
-- Instantiate the Unit Under Test (UUT)
------------------------------------------------------
uut: compress_decompress_top PORT MAP(
CLK => CLK,
RST => RST,
ENA => ENA,
cmode => cmode,
xin => xin,
xout => xout);

Clocket : process --100 MHz -> T = 10 ns
begin
CLK <= '1';
wait for 50 ns;
CLK <= '0';
wait for 50 ns;
end process;

RST <= '1', '0' after 90 ns;
ENA <= '0', '1' after 95 ns ;
cmode <= "0110010";


-- Read from stimulus file and apply to circuit process
-------------------------------------------------------
Process_1 : PROCESS
FILE Stimulus_File : TEXT;
FILE Results_File : TEXT;
VARIABLE Input_Pattern : LINE;
VARIABLE Results_Pattern : LINE;
VARIABLE Read_OK : BOOLEAN;
VARIABLE Char : CHARACTER;
VARIABLE x_In : INTEGER;
Variable x_Out : INTEGER;
--------------------------------------

BEGIN

--------------------------------------
-- Open files for READ and WRITE
--------------------------------------
FILE_OPEN(Stimulus_File, "Circuit1_Stimulus.txt", READ_MODE);
FILE_OPEN(Results_File, "Circuit1_Results.txt", WRITE_MODE);

--------------------------------------
-- Write header text to results file
--------------------------------------
WRITE(Results_Pattern, "-----------------------------");
WRITELINE(Results_File, Results_Pattern);
WRITE(Results_Pattern, "xin xout");
WRITELINE(Results_File, Results_Pattern);
WRITE(Results_Pattern, "-----------------------------");
WRITELINE(Results_File, Results_Pattern);
--------------------------------------
-- Loop read from file and apply
-- stimulus until end of file
--------------------------------------
IF (RST='1') THEN
xin <= "00000000";
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENA = '1') THEN

WHILE (NOT ENDFILE(Stimulus_File)) LOOP
--------------------------------------
-- Read line from 'Stimulus_File' into
-- variable 'Input_Pattern'
--------------------------------------
READLINE(Stimulus_File, Input_Pattern);
--------------------------------------
-- Read first character from
-- 'Input_Pattern'
--------------------------------------
READ(Input_Pattern, CHAR, Read_OK);
--------------------------------------
-- If line is not good or the first
-- character is not a TAB, then
-- skip remainder of loop is not good
--------------------------------------
IF((NOT Read_OK) OR (CHAR /=HT)) THEN NEXT;
END IF;
--------------------------------------
-- Read first stimulus bit
-- Read second stimulus bit
-- Read third stimulus bit
--------------------------------------
READ(Input_Pattern, x_In);
READ(Input_Pattern, CHAR);
--------------------------------------
-- Apply test stimulus
-- Initially convert inputs (A, B, C)
-- as BIT_VECTOR to STD_LOGIC_VECTOR
--------------------------------------
xin <= To_Stdlogicvector(int2bit_vec(x_in, 8));
--------------------------------------
-- Wait for time before applying next
-- test stimulus
--------------------------------------
WAIT FOR 100 ns;
--------------------------------------
-- Convert 'Z' STD_LOGIC to 'Z_Out'
-- BIT – only consider logic '0' and
-- logic '1' and unknown 'X'
--------------------------------------
x_out := CONV_INTEGER (xout);
--------------------------------------
-- Write stimulus and output to output
-- file
--------------------------------------
WRITE(Results_Pattern, x_In);
WRITE(Results_Pattern, " ");
WRITE(Results_Pattern, x_Out);
WRITELINE(Results_File, Results_Pattern);
--------------------------------------
-- End of Loop
--------------------------------------
END LOOP;
END IF ;
END IF ;

--------------------------------------
-- Write footer text to results file
--------------------------------------
WRITE(Results_Pattern, "-----------------------------");
WRITELINE(Results_File, Results_Pattern);
WRITE(Results_Pattern, "-- Test completed");
WRITELINE(Results_File, Results_Pattern);
WRITE(Results_Pattern, "-----------------------------");
WRITELINE(Results_File, Results_Pattern);
--------------------------------------
-- Close the OPENed files
--------------------------------------
FILE_CLOSE(Stimulus_File);
FILE_CLOSE(Results_File);
--------------------------------------
-- Stop process or it will repeat if
-- simulation time longer than a
-- single pass of the input and will
-- overwrite results file
--------------------------------------
WAIT;
--------------------------------------
END PROCESS;
------------------------------------------------------
END ARCHITECTURE Behavioural;
------------------------------------------------------------------
-- End of File
------------------------------------------------------------------

And my text file is :
 

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  • Circuit1_Stimulus.txt
    134 KB · Views: 8

TrickyDicky

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What problems are you having?

Theres certainly a lot of redundant code and VHDL misunderstandings, but it should work.
 

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