My problem in clock forwarding

[mk14]

Hello all;
I'm trying to create a 30 MHz clock from an external 25 MHz crystal oscillator by Spartan 6 lx9 144.
My simulations are OK, but when implementing in ISE, I face this famous error:
---------------------------------------------------------------------------------
ERRORlace:1205 - This design contains a global buffer instance,
<Ins/clkout1_buf>, driving the net, <Output_Clock_OBUF>, that is driving the
following (first 30) non-clock load pins off chip.
< PIN: Output_Clock.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.


ERRORlace:1136 - This design contains a global buffer instance,
<Ins/clkout1_buf>, driving the net, <Output_Clock_OBUF>, that is driving the
following (first 30) non-clock load pins.
< PIN: Output_Clock.O; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "Ins/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >


ERRORack:1654 - The timing-driven placement phase encountered an error.
---------------------------------------------------------------------------------

I used ODDR2 in the following way (this is my whole code.). But, I still receive the same error.
Can somebody help me, please?

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
module myDCM(
    input   Input_Clock,
    input   Reset,
    output  Output_Clock,
    output  Locked,
    output  Clock_Valid
    );
     
     CLK_MDFR_CORE Ins
   (
    .CLK_IN(Input_Clock), 
    .CLK_OUT(Output_Clock),  
    .RESET(Reset),
    .LOCKED(Locked),
    .CLK_VALID(Clock_Valid)
     );
     
     
    // Clock forwarding circuit using the double data-rate register
  //        Spartan-3E/3A/6
 // Xilinx HDL Language Template, version 14.7
 
   ODDR2 ODDR2Ins(
      .DDR_ALIGNMENT("C0"), // Sets output alignment to "NONE", "C0" or "C1" 
      .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
      .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
            )
            
        clock_forward (
      .Q(CLK),                // 1-bit DDR output data
      .C0(Output_Clock),      // 1-bit clock input
      .C1(~Output_Clock),     // 1-bit clock input
      .CE(1'b1),                        // 1-bit clock enable input
      .D0(1'b1),              // 1-bit data input (associated with C0)
      .D1(1'b0),              // 1-bit data input (associated with C1)
      .R(1'b0),                         // 1-bit reset input
      .S(1'b0)                      // 1-bit set input
   );
 
   // End of clock_forward_inst instantiation
 
 
endmodule

---

 

[vGoodtimes]

module myDCM(
input	Input_Clock,
input	Reset,
output	Output_Clock, // This is the output clock
output	Locked,
output	Clock_Valid
);

CLK_MDFR_CORE Ins
(
.CLK_IN(Input_Clock), 
.CLK_OUT(Output_Clock), // This is NOT the output clock.  This is an intermediate clock
.RESET(Reset),
.LOCKED(Locked),
.CLK_VALID(Clock_Valid)
);

// snip
ODDR2 ODDR2Ins
clock_forward (
.Q(CLK), // 1-bit DDR output data // This is the output clock
.C0(Output_Clock), // 1-bit clock input // This is the intermediate clock
.C1(~Output_Clock), // 1-bit clock input // this is the intermediate clock complement.
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);

 

[mk14]

Thank you.
In fact, I have a more fundamental question:
Is the code above the whole thing I need to use the DCM in Spartan 6? (I mean to implement it)
I developed a tester and a test fixture and simulated it and it was completely OK.

 

[ads-ee]

Thank you.
In fact, I have a more fundamental question:
Is the code above the whole thing I need to use the DCM in Spartan 6? (I mean to implement it)
I developed a tester and a test fixture and simulated it and it was completely OK.

Because it was only a simulation and the implementation tools are the ones complaining about it. If you did this in a Virtex 7 you wouldn't see any errors, but since you are using Spartan 6 they don't have dedicated routing to run a clock off a global buffer to a pin output buffer.

vGoodtimes was expecting you to figure out from their clue you've got the wrong connections to the various ports, hence the error is still there.

Change this:

---

Code Verilog - [expand]
1
2
3
4
5
6
// module output port
 output Output_Clock,
// oddr2 instance
      .Q(CLK),                // 1-bit DDR output data
      .C0(Output_Clock),      // 1-bit clock input
      .C1(~Output_Clock),     // 1-bit clock input

---

to this

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
// module output port
 output Output_Clock,
// clock DCM output
.CLK_OUT(local_clock),
// oddr2 instance
      .Q(Output_Clock),                // 1-bit DDR output data
      .C0(local_clock),      // 1-bit clock input
      .C1(~local_clock),     // 1-bit clock input

---