tony_taoyh
Full Member level 2
two stage or three stage synchronizer
The following is my tips, during my design of digital IC.
If you think it is useful to you, please donate me some points.
Because I want to download some materials.
If you think it is still good, I will post the rest part,
such as vi tips, DC tips, apollo tips.
Also the notes when I read through the following manuals:
(1) DC (2) Power compile;
(3) Lib compiler; (4) Astro and Apollo;
(5) Cadence SOC.
One words, network = sharing.
Thanks a lot.
Best Regards,
Tony
------------------------------------------------------------------
1.
However, a two-stage synchronizer circuit is sufficient to avoid metastability in
multiple clock designs. A three-stage synchronizer is required in designs where
the clock frequencies are very high.
2. data between two clock domain:
1) hand shake:
¡°Latency¡± for a single data transfer from one clock domain to other is much
more than that of a FIFO used for the same data transfer.
2) FIFO.
3) v2lvs -i: verilog to spice...
v2lvs -i -v ../lvdmt.sv -o lvdmt.cir -s0 "VSS" -s1 "VDD" -lsp san_25.lib -a _
4) The reason to set max_transition:
In STA, the timing is from 2-D look-up table,
One D is transition timing,
So if the transition is too big, then the transition is out of
the range of the look up table, then the linear extrapolation
must be used. SO the result is not accurate.
5) gated clock:
We need to consider the distance between the clock port and gated cell.
6) set_clock_transition, for ideal clock network.
Which overide the calculated transition.
In both DC and PT, if set_propagated_clock is set, then
set_clock_transition will be ignored.
7) vcd2vec
/cadapps/SNPS/NanoSim/Solaris/03.12/sparcOS5/ns/bin/vcd2vec -nvcd input.vcd -nvec out.vec
8) We can use Calibre to get gate level RC netlist, spef format,
Then we can use it for STA.
9) After Synchronization, the reset is no longer false path,
we need to consider the recovery and removal timing check.
10)
TSMC does not allow input tie to VDD and VSS directly. I realise that
there is 1'b0 and 1'b1 in the netlist. In my previous project, I am not
able to use encounter command (bug?) to replace this with connection to
TIEHI and TIELO cells in the library.
11) Why need fill metal?
Use dummy fills to reduce skew by reducing variations in interconnect capacitances due to interlayer dielectric thickness variations.
12) We "set timing_self_loop_no_skew false". We used to have this switch
set true in our common start up scripts with no serious impact on
our runtimes. Somewhere along the way, this changed. Having this switch set true dramatically increases runtimes.
13) Changed our scan insertion flow from "insert_scan" to "insert_dft".
We use "set dft_optimization_configuration -none -preserve true".
This eliminates designs from being duplicated in memory with a "_test" name. This yields a sizeable reduction in required memory when doing scan insertion.
14)
Our current top down DC Nighthawk2 script does the following:
1) Analyze/Elaborate the RTL
2) Constrain the design and do a "compile". Generate reports.
3) Insert scan (using insert_dft). Generate reports.
4) Constrain the design and do a compile -inc. Generate reports.
15) For the Gated loagical; it is better to use instantance,
then "set_dont_touch" attribute on it.
16) For UNIX, in .cshrc:
If two folders include same command but with different version,
To use the latest one, should put the folder with new one
at the latter part of the search_path.
That is to say, for the new one, add it at below.
17) Some library may have: Metastable-hardened D flip-flops.
If it is, use them for the first stage of the synchronizer.
18) One urgent error in colloie project:
"I checked your STA script and found you are specify
"set_case_analysis 1 test_se"
and this means this STA condition is only for scan serial mode,
not including scan capture mode of "test_se = low" case."
So in scan mode, should not put test_se as 0.
19) Verilog data type:
real serial_period;
integer serial_period;
20) real in verilog:
module tt;
real a;
real b;
initial
begin
a = 11.1;
b = a/2;
$display("%f,%f",a,b);
$finish;
end
endmodule
11.100000,5.550000
But we can not use top.xxx_inst_a in another module.
21) We need to find a way to check those DFF without reset/
22) It is better to use a BUFFER between the DFF output and chip output.
So need to find a way to control it.
23)
It is for this
reason that high-fanout nets should be labled don't touched
during synthesis in Design Compiler and synthesis should be
left to a back-end tool like Physical Compiler or Astro.
24) to check all DFFs without Reset, use one perl program:
#!/usr/bin/perl
open(INFER_REP, "$ARGV[0]") || die ("Could not open input inference logfile");
#open files to place each inferred register into a proper category
open(ASYNC_RES, ">async_reset.txt");
open(ASYNC_SET, ">async_set.txt");
open(SYNC_RES, ">sync_reset.txt");
open(SYNC_SET, ">sync_set.txt");
open(NO_SYNC, ">no_set_reset.txt");
$_ = <INFER_REP>;
while ($_ ne "") {
#look through logfile for Inference tables
if ($_ =~ /Inferred.+/) {
#parse extraneous lines
$_ = <INFER_REP>;
$_ = <INFER_REP>;
$_ = <INFER_REP>;
$_ = <INFER_REP>;
$_ = <INFER_REP>;
#process each line in table, table ends at "="
if ($_ =~ /\=.+/) {
$_ = <INFER_REP>;
while ($_ !~ /=.+/) {
#| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
/\|\s+(\S+)\s+\|\s+\S+\s+\|\s+(\d+)\s+\|\s+\S+\s+\|\s+\S+\s+\|\s+(\S+)\s+\|\s+(\S+)\s+\|\s+(\S+)\s+\|\s+(\S+)\s+\|\s+\S+/;
#add register name to appropriate category file
if ($3 eq "Y") { printf ASYNC_RES ("%s\n", $1); }
if ($4 eq "Y") { printf ASYNC_SET ("%s\n", $1); }
if ($5 eq "Y") { printf SYNC_RES ("%s\n", $1); }
if ($6 eq "Y") { printf SYNC_SET ("%s\n", $1); }
if (($3 eq "N") && ($4 eq "N") && ($5 eq "N") && ($6 eq "N"))
{ printf NO_SYNC ("%s\n", $1); }
$_ = <INFER_REP>;
}
}
}
$_ = <INFER_REP>;
}
25) Bi-Direction Port in Verilog:
input A, B, C;
output D;
inout E;
wire D, E;
...
assign E = oe ? A : 1'bz;
assign D = B & E;
...
endmodule
26) Verilog strength:
| Strength | Name | Keyword(s) |
| Level | | |
=================================================
| 7 | Supply Drive | supply0 supply1 |
| 6 | Strong Drive | strong0 strong1 |
| 5 | Pull Drive | pull0 pull1 |
| 4 | Large Capacitive | large |
| 3 | Weak Drive | weak0 weak1 |
| 2 | Med. Capacitive | medium |
| 1 | Small Capacitive | small |
| 0 | High Impedance | highz0 highz1 |
=================================================
module test;
wire strong_wire;
wire weak_wire;
assign (weak0, weak1) weak_wire = strong_wire;
//now connect strong_wire to the output of other modules
endmodule
27) From V-2003.12, for the Prime time, there is one command for
error and warning checks:
pt_shell> print_message_info
28) error_info: Prime Time,
Can use this command to check the last error.
29) Why do report_constraint and report_timing report different transition times?
The command report_constraint -max_transition reports the worst possible
transition time on a pin, whereas the command report_timing -transition
reports the timing path having the worst slack. For the worst-slack path,
the transition time on a particular pin depends on the path taken through
the pin.
30) In DC and PT, use: report_timing > tt.txt
Then the result will not display in the log files,
so some warnings may be ignore.
So we must pay attention to both log file and report file.
Do not let any warning and information gone.
31) Information: Expanding clock 'ssc' to base period of 5.00
(old period was 2.50, added 2 edges). (PTE-016)
When multiple clocks interact, PrimeTime expands the related clocks to a common
base period, which is smallest period over which all of the clock frequencies
are periodic. In other words, it is the smallest number divisible by all the
clock periods. PrimeTime expands each of the clocks to a maximum of one
thousand times to determine this common base.
32) Tips: Use a small design for try.
If the original design is too large to load or run.
33) For the sync of reset net:
reg reset_clk_1;
reg reset_clk;
always @(posedge clk or negedge reset)
begin
if (~reset)
begin
reset_clk_1 <= 1'b0;
reset_clk <= 1'b0;
end
else
begin
reset_clk_1 <= 1'b1;
reset_clk <= reset_clk_1;
end
end
In the STA and DC timing report, the net from D to CP
will be considered as "disable_timing", because
it is start from the constant 1.
34) for message information:
echo -n "The Error Message Number: " > ../report/get_message_info.rpt
get_message_info -error_count >> ../report/get_message_info.rpt
echo -n "The Warning Message Number: " >> ../report/get_message_info.rpt
get_message_info -warning_count >> ../report/get_message_info.rpt
echo -n "The Info Message Number: " >> ../report/get_message_info.rpt
get_message_info -info_count >> ../report/get_message_info.rpt
#For PT V2003.12 or Later
#echo " "
#echo " "
#echo "***************************************************"
#print_message_info
35) For the reset after sync,
assign RSTN_412_OUT = SCAN_MODE ? 1'b1 : RSTN_412_SYNC3;
Some times, 1'b1 is used for SCAN mode,
but some times, it is needed from the RSTNIN.,,,input port..
36) In PT, if the input file is SPEF.
then we can use the built-in delay calcultor,
and we also can use:
write_sdf -significant_digits 4 tt.sdf
The result is same as sign-off delay calcultor.
For the net delay for rising or falling,
min corner and max cornor, the net delay should be same.
But for cell delay, it is different.
37) Usually, we need to set clock uncertainty for worst case
(setup time) and best case seperately:
for example: 0.2 for setup timing;
0.1 for hold timing;
38) The cap for pcb board and physical pad is about 4 pf.
39) It is not good to quote the nets of RTL in the tesetbench;
Drawback: During synthesis, the hierarchy need to be kept,
to let the original simulation environment to use old setup.
It is better to use a port to output it to top level.
40) When do not use flat design:
(1) For subblock, need to dissolve the hierarchy infered by the MUX,
ADD,
(2) In DC, this will be done auto.
(3) In ambit, some variable will also enable auto.
41. Ambit:
set_global aware_dissolve_width 1000
set_global aware_mux_dissolve_size 4
to auto disolve the hierarchy.
The following is my tips, during my design of digital IC.
If you think it is useful to you, please donate me some points.
Because I want to download some materials.
If you think it is still good, I will post the rest part,
such as vi tips, DC tips, apollo tips.
Also the notes when I read through the following manuals:
(1) DC (2) Power compile;
(3) Lib compiler; (4) Astro and Apollo;
(5) Cadence SOC.
One words, network = sharing.
Thanks a lot.
Best Regards,
Tony
------------------------------------------------------------------
1.
However, a two-stage synchronizer circuit is sufficient to avoid metastability in
multiple clock designs. A three-stage synchronizer is required in designs where
the clock frequencies are very high.
2. data between two clock domain:
1) hand shake:
¡°Latency¡± for a single data transfer from one clock domain to other is much
more than that of a FIFO used for the same data transfer.
2) FIFO.
3) v2lvs -i: verilog to spice...
v2lvs -i -v ../lvdmt.sv -o lvdmt.cir -s0 "VSS" -s1 "VDD" -lsp san_25.lib -a _
4) The reason to set max_transition:
In STA, the timing is from 2-D look-up table,
One D is transition timing,
So if the transition is too big, then the transition is out of
the range of the look up table, then the linear extrapolation
must be used. SO the result is not accurate.
5) gated clock:
We need to consider the distance between the clock port and gated cell.
6) set_clock_transition, for ideal clock network.
Which overide the calculated transition.
In both DC and PT, if set_propagated_clock is set, then
set_clock_transition will be ignored.
7) vcd2vec
/cadapps/SNPS/NanoSim/Solaris/03.12/sparcOS5/ns/bin/vcd2vec -nvcd input.vcd -nvec out.vec
8) We can use Calibre to get gate level RC netlist, spef format,
Then we can use it for STA.
9) After Synchronization, the reset is no longer false path,
we need to consider the recovery and removal timing check.
10)
TSMC does not allow input tie to VDD and VSS directly. I realise that
there is 1'b0 and 1'b1 in the netlist. In my previous project, I am not
able to use encounter command (bug?) to replace this with connection to
TIEHI and TIELO cells in the library.
11) Why need fill metal?
Use dummy fills to reduce skew by reducing variations in interconnect capacitances due to interlayer dielectric thickness variations.
12) We "set timing_self_loop_no_skew false". We used to have this switch
set true in our common start up scripts with no serious impact on
our runtimes. Somewhere along the way, this changed. Having this switch set true dramatically increases runtimes.
13) Changed our scan insertion flow from "insert_scan" to "insert_dft".
We use "set dft_optimization_configuration -none -preserve true".
This eliminates designs from being duplicated in memory with a "_test" name. This yields a sizeable reduction in required memory when doing scan insertion.
14)
Our current top down DC Nighthawk2 script does the following:
1) Analyze/Elaborate the RTL
2) Constrain the design and do a "compile". Generate reports.
3) Insert scan (using insert_dft). Generate reports.
4) Constrain the design and do a compile -inc. Generate reports.
15) For the Gated loagical; it is better to use instantance,
then "set_dont_touch" attribute on it.
16) For UNIX, in .cshrc:
If two folders include same command but with different version,
To use the latest one, should put the folder with new one
at the latter part of the search_path.
That is to say, for the new one, add it at below.
17) Some library may have: Metastable-hardened D flip-flops.
If it is, use them for the first stage of the synchronizer.
18) One urgent error in colloie project:
"I checked your STA script and found you are specify
"set_case_analysis 1 test_se"
and this means this STA condition is only for scan serial mode,
not including scan capture mode of "test_se = low" case."
So in scan mode, should not put test_se as 0.
19) Verilog data type:
real serial_period;
integer serial_period;
20) real in verilog:
module tt;
real a;
real b;
initial
begin
a = 11.1;
b = a/2;
$display("%f,%f",a,b);
$finish;
end
endmodule
11.100000,5.550000
But we can not use top.xxx_inst_a in another module.
21) We need to find a way to check those DFF without reset/
22) It is better to use a BUFFER between the DFF output and chip output.
So need to find a way to control it.
23)
It is for this
reason that high-fanout nets should be labled don't touched
during synthesis in Design Compiler and synthesis should be
left to a back-end tool like Physical Compiler or Astro.
24) to check all DFFs without Reset, use one perl program:
#!/usr/bin/perl
open(INFER_REP, "$ARGV[0]") || die ("Could not open input inference logfile");
#open files to place each inferred register into a proper category
open(ASYNC_RES, ">async_reset.txt");
open(ASYNC_SET, ">async_set.txt");
open(SYNC_RES, ">sync_reset.txt");
open(SYNC_SET, ">sync_set.txt");
open(NO_SYNC, ">no_set_reset.txt");
$_ = <INFER_REP>;
while ($_ ne "") {
#look through logfile for Inference tables
if ($_ =~ /Inferred.+/) {
#parse extraneous lines
$_ = <INFER_REP>;
$_ = <INFER_REP>;
$_ = <INFER_REP>;
$_ = <INFER_REP>;
$_ = <INFER_REP>;
#process each line in table, table ends at "="
if ($_ =~ /\=.+/) {
$_ = <INFER_REP>;
while ($_ !~ /=.+/) {
#| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
/\|\s+(\S+)\s+\|\s+\S+\s+\|\s+(\d+)\s+\|\s+\S+\s+\|\s+\S+\s+\|\s+(\S+)\s+\|\s+(\S+)\s+\|\s+(\S+)\s+\|\s+(\S+)\s+\|\s+\S+/;
#add register name to appropriate category file
if ($3 eq "Y") { printf ASYNC_RES ("%s\n", $1); }
if ($4 eq "Y") { printf ASYNC_SET ("%s\n", $1); }
if ($5 eq "Y") { printf SYNC_RES ("%s\n", $1); }
if ($6 eq "Y") { printf SYNC_SET ("%s\n", $1); }
if (($3 eq "N") && ($4 eq "N") && ($5 eq "N") && ($6 eq "N"))
{ printf NO_SYNC ("%s\n", $1); }
$_ = <INFER_REP>;
}
}
}
$_ = <INFER_REP>;
}
25) Bi-Direction Port in Verilog:
input A, B, C;
output D;
inout E;
wire D, E;
...
assign E = oe ? A : 1'bz;
assign D = B & E;
...
endmodule
26) Verilog strength:
| Strength | Name | Keyword(s) |
| Level | | |
=================================================
| 7 | Supply Drive | supply0 supply1 |
| 6 | Strong Drive | strong0 strong1 |
| 5 | Pull Drive | pull0 pull1 |
| 4 | Large Capacitive | large |
| 3 | Weak Drive | weak0 weak1 |
| 2 | Med. Capacitive | medium |
| 1 | Small Capacitive | small |
| 0 | High Impedance | highz0 highz1 |
=================================================
module test;
wire strong_wire;
wire weak_wire;
assign (weak0, weak1) weak_wire = strong_wire;
//now connect strong_wire to the output of other modules
endmodule
27) From V-2003.12, for the Prime time, there is one command for
error and warning checks:
pt_shell> print_message_info
28) error_info: Prime Time,
Can use this command to check the last error.
29) Why do report_constraint and report_timing report different transition times?
The command report_constraint -max_transition reports the worst possible
transition time on a pin, whereas the command report_timing -transition
reports the timing path having the worst slack. For the worst-slack path,
the transition time on a particular pin depends on the path taken through
the pin.
30) In DC and PT, use: report_timing > tt.txt
Then the result will not display in the log files,
so some warnings may be ignore.
So we must pay attention to both log file and report file.
Do not let any warning and information gone.
31) Information: Expanding clock 'ssc' to base period of 5.00
(old period was 2.50, added 2 edges). (PTE-016)
When multiple clocks interact, PrimeTime expands the related clocks to a common
base period, which is smallest period over which all of the clock frequencies
are periodic. In other words, it is the smallest number divisible by all the
clock periods. PrimeTime expands each of the clocks to a maximum of one
thousand times to determine this common base.
32) Tips: Use a small design for try.
If the original design is too large to load or run.
33) For the sync of reset net:
reg reset_clk_1;
reg reset_clk;
always @(posedge clk or negedge reset)
begin
if (~reset)
begin
reset_clk_1 <= 1'b0;
reset_clk <= 1'b0;
end
else
begin
reset_clk_1 <= 1'b1;
reset_clk <= reset_clk_1;
end
end
In the STA and DC timing report, the net from D to CP
will be considered as "disable_timing", because
it is start from the constant 1.
34) for message information:
echo -n "The Error Message Number: " > ../report/get_message_info.rpt
get_message_info -error_count >> ../report/get_message_info.rpt
echo -n "The Warning Message Number: " >> ../report/get_message_info.rpt
get_message_info -warning_count >> ../report/get_message_info.rpt
echo -n "The Info Message Number: " >> ../report/get_message_info.rpt
get_message_info -info_count >> ../report/get_message_info.rpt
#For PT V2003.12 or Later
#echo " "
#echo " "
#echo "***************************************************"
#print_message_info
35) For the reset after sync,
assign RSTN_412_OUT = SCAN_MODE ? 1'b1 : RSTN_412_SYNC3;
Some times, 1'b1 is used for SCAN mode,
but some times, it is needed from the RSTNIN.,,,input port..
36) In PT, if the input file is SPEF.
then we can use the built-in delay calcultor,
and we also can use:
write_sdf -significant_digits 4 tt.sdf
The result is same as sign-off delay calcultor.
For the net delay for rising or falling,
min corner and max cornor, the net delay should be same.
But for cell delay, it is different.
37) Usually, we need to set clock uncertainty for worst case
(setup time) and best case seperately:
for example: 0.2 for setup timing;
0.1 for hold timing;
38) The cap for pcb board and physical pad is about 4 pf.
39) It is not good to quote the nets of RTL in the tesetbench;
Drawback: During synthesis, the hierarchy need to be kept,
to let the original simulation environment to use old setup.
It is better to use a port to output it to top level.
40) When do not use flat design:
(1) For subblock, need to dissolve the hierarchy infered by the MUX,
ADD,
(2) In DC, this will be done auto.
(3) In ambit, some variable will also enable auto.
41. Ambit:
set_global aware_dissolve_width 1000
set_global aware_mux_dissolve_size 4
to auto disolve the hierarchy.