scanning flip flop
Question 1 is still NOT solved!!!
I checked spf file. Timing section and waveform table exsits.
I read synopsys document and found following sentence:
"after insert_dft, the initialization sequence is lost. You must reapply the same initialization sequence to ensure that post-scan insertion test DRC reports no violations."
Yes, in my question 1, the violation ocurred only at the last dft_drc, which is after insert_dft. And original warning prompt "Warning: Input force of chain c0 must be loaded by first cocking of in_reg1_reg (S6-1)" just complains that test_si/primary input need to be load before 1st clock.
How should I modify my script? I just set test clock, async. rst, and scan enable attribute for design. Then insert scan. Is there any other steps need to be done? reapply test_setup? How to? Or need to add patterns in spf?
But why everything is right for dft_drc before insert_dft?
Could somebody give me some help?
Thanks a lot!
Added after 53 minutes:
I got it, finally!
Now everything is ok, and the log file looks so beautiful! Have a nice day!