akp494
Member level 1
Hi
In my RTL I have two clocks going as an input to a MUX. One is 500 MHz clock and another is 12 MHz. When select line of MUX is '0' then 500 MHz clock is selected. The MUX output is supplied as clock to some of the modules.
Here are the few observations I made when i did synthesis using DC on this design.
1) First time I didn't tell the tool that there is clock gating in my design. But I specified both the clocks. DC didn't report any timing violations. Area came around 53 K. Non-Combinational area being 24K and the rest is combinational area. But I can see both 500 MHz and 12 MHz clock groups in the timing report.
2) Second time I removed the MUX from RTL and connected 500 MHz clock directly to all the modules and synthesized the design. There were no timing violations reported but surprisingly area went upto 90K which I think is huge increase.
3) Third time I hard instantiated the MUX cell in the RTL . This MUX cell was taken from the target library. I synthesized this design and used set_case_analysis. I did a case analysis by setting the select line value to '0' so that 500 MHz clock is selected. Now also there are no timing violations reported but area came around 78K.
In all the above cases non-combinational area remained the same at 24K. Only combinational area was changing.
I am really confused with these strange results from DC. Can someone please explain me why these strange results are reported by DC .
Thanks in advance.
Prasad
In my RTL I have two clocks going as an input to a MUX. One is 500 MHz clock and another is 12 MHz. When select line of MUX is '0' then 500 MHz clock is selected. The MUX output is supplied as clock to some of the modules.
Here are the few observations I made when i did synthesis using DC on this design.
1) First time I didn't tell the tool that there is clock gating in my design. But I specified both the clocks. DC didn't report any timing violations. Area came around 53 K. Non-Combinational area being 24K and the rest is combinational area. But I can see both 500 MHz and 12 MHz clock groups in the timing report.
2) Second time I removed the MUX from RTL and connected 500 MHz clock directly to all the modules and synthesized the design. There were no timing violations reported but surprisingly area went upto 90K which I think is huge increase.
3) Third time I hard instantiated the MUX cell in the RTL . This MUX cell was taken from the target library. I synthesized this design and used set_case_analysis. I did a case analysis by setting the select line value to '0' so that 500 MHz clock is selected. Now also there are no timing violations reported but area came around 78K.
In all the above cases non-combinational area remained the same at 24K. Only combinational area was changing.
I am really confused with these strange results from DC. Can someone please explain me why these strange results are reported by DC .
Thanks in advance.
Prasad