Must describe in a ROM in vhdl

[sorinel]

hello all
I am a student and I need to describe a ROM in vhdl ,but the program has too many unknowns for me. Please give me some ideas.
ROM has 64 addresses and each address is stored in a 6-bit value
which is the product of two numbers defined by 3 bits address bus. The two
3-bit numbers are given by the 6 bits of the address entry as follows: A (5 downto 3) and A (2
downto 0). For example, at '51 '(110 011 in binary) is stored the number '18' (010,010 in binary) as A (5 downto 3) = 110 ('6 'in decimal), A (2 downto 0) = 011 ('3' in decimal) and
110 * 011 = 010 010 (6 * 3 ​​= 18 in decimal).
Thanks. any help is appreciated

 

[TrickyDicky]

Why do you need a rom? what cant you just use mulitpliers?

 

[treqer]

no-no-no
I realized that he needed to fill the table number associated with the address or to each other by multiplying

 

[sorinel]

Must describe a rom for my teacher wants it.Is important to respect the requirements.Since a couple of days I've been researching but I wasn't able to describe the ROM.I don't know what to do?
Thanks!

 

[sorinel]

I belive that I can describe a multiplier using a ROM.
The circuit's ports are: A[5:0]-input, which
is a bus for adresses, D[5:0]-output which is a bus for data
informations and it gets the data value which is stored at the adress
of the input A ;OE(output enable) -it is the input which activates the
output D- if OE='1' then at the out D it will be the value which is
stored in the memory, or else, the bits of output D will be in a state
of high impedance; CS (circuit select)- activation input of circuit. if
CS='1' the circuit will decode the adress input and will supply the
output (if OE='1') value stored at the specified address.else (if
CS='0'), the circuit will not decode adress input, and at output D the
bits will be in a state of high impedance.
Thanks for previous answers.

 

[FvM]

A ROM in VHDL doesn't necessarily have the control lines of a ROM chip, but of course, it can have them if you want to model a particular device. If so, the requirements should be specified, but you didn't tell about.

On the other hand, a ROM in VHDL can be simply an initialized array of constants. Possibly the solution of your exercise should show it.

Finally, different kinds of behavioral code can be implemented by the synthesisis tool as a ROM. But you dont necessarily see it from the code.

 

[sorinel]

I must describe a multiplier based on a ROM. And the requirements are:ROM has 64 addresses and each address is stored in a 6-bit valuewhich is the product of two numbers defined by 3 bits address bus. The two
3-bit numbers are given by the 6 bits of the address entry as follows: A (5 downto 3) and A (2
downto 0). For example, at '51 '(110 011 in binary) is stored the number '18' (010,010 in binary) as A (5 downto 3) = 110 ('6 'in decimal), A (2 downto 0) = 011 ('3' in decimal) and
110 * 011 = 010 010 (6 * 3 ​​= 18 in decimal).
And the circuit's port are:A[5:0]-input, which
is a bus for adresses, D[5:0]-output which is a bus for data
informations and it gets the data value which is stored at the adress
of the input A ;OE(output enable) -it is the input which activates the
output D- if OE='1' then at the out D it will be the value which is
stored in the memory, or else, the bits of output D will be in a state
of high impedance; CS (circuit select)- activation input of circuit. if
CS='1' the circuit will decode the adress input and will supply the
output (if OE='1') value stored at the specified address.else (if
CS='0'), the circuit will not decode adress input, and at output D the
bits will be in a state of high impedance.
I must implement a behavioral model based on memory multiplier
ROM described above and a testbench for simulation and verification circuit. My english is not sow good and I apologize for this.
Thank you for your attention !

 

[FvM]

A behavioral model actually don't need to implement a memory, it would only need a description like below. Properties of a real device, e.g. transport delays can be implemented according to a specification:

D <= std_logic_vector(unsigned(A(5 downto 3)*unsigned(A(2 downto 0)) when CS and OE = '1'
else (others => 'Z');

 

[permute]

A rom can also be implemented using a constant. eg:

type mrom_type is array(63 downto 0) of std_logic_vector(5 downto 0);
constant MROM : mrom_type := ("101010", "101010", ...) ;
--example values, not calculated.
...
mult <= MROM(to_integer(unsigned({arg1,arg2})));

 

[sorinel]

This ai describe :
library ieee;
use ieee.std_logic_1164.all;

entity ROM is
port ( address_A : in std_logic_vector(5 downto 0);
data_D : out std_logic_vector(5 downto 0)
CS,CS:in BIT ;
end entity ROM;

architecture behavioral of ROM is
type mem is array ( 63 to 0) of std_logic_vector(5 downto 0);
constant my_Rom : mem := (
0 => "000000",
1 => "000000",
2 => "000000",
3 => "000000",
4 => "000000",
5 => "000000",
6 => "000000",
7 => "000000",
8 => "000000",
9 => "000001", "(9in binar is 001001 and the number located is 1)
10 =>"000010",
....to 63......);
begin
process (address)
begin
if CS and OE = '1'then
case address is
when "0000" => data <= my_rom(0);
when "0001" => data <= my_rom(1);
when "0010" => data <= my_rom(2);
when "0011" => data <= my_rom(3);
when "0100" => data <= my_rom(4);
when "0101" => data <= my_rom(5);
when "0110" => data <= my_rom(6);
when "0111" => data <= my_rom(7);
when "1000" => data <= my_rom(8);
when "1001" => data <= my_rom(9);
when "1010" => data <= my_rom(10);
.....to 63....
when others => data <= "00000000";
end case;
else
data <= 'Z';
end process;
end architecture behavioral;
How can I create a function for "my_rom"(used by me in program)?

Thank for all answer!!!

---------- Post added at 23:19 ---------- Previous post was at 23:17 ----------

I need a concrete function......
Thanks!

---------- Post added at 23:46 ---------- Previous post was at 23:19 ----------

Please help me make this program better based on this model.
Thanks!

 

[TrickyDicky]

if you include the numeric_std package, you dont need that large case statement to access the rom, you can just write:

data <= my_rom( to_integer( unsigned( address) ) );

 

[lucbra]

The whole issue is not the desciption of the ROM but filling the ROM with the correct data

 

[FvM]

The whole issue is not the desciption of the ROM but filling the ROM with the correct data

Yes. Strictly spoken, a memory array is useless for a ROM simulation model, because it can use a simple behavioral expression as well, as suggested before.

Secondly, the construct

case address is
when "0000" => data <= my_rom(0);
when "0001" => data <= my_rom(1);

is completely superfluous, even if you want to use a real ROM in your simulation code for arbitrary reasons. A single line can be used instead of 64 cases:

data <= my_rom(to_integer(unsigned(address)));

Finally, the ROM initialization can be most simply done by function. Alternatively, a special generate syntax can calculate the values at compilation time. As said, it's not actually needed for a simulation model. But in hardware synthesis, it's the way to initialize a ROM in pure VHDL, without external tools.

P.S.: A reference to the generate initialization method. Of course the calculation is different (more simple) in this case:
https://www.edaboard.com/threads/117304/#post512742

 

[FvM]

when I try to compile it I have some errors

I feel like in a guessing game.