[SOLVED] Multiply driven in VHDL

I am learning VHDL now. I can't understand this "multiply driven" concept. See the code below


The compiler complains that the accum is multiply driven.

What do you mean by this "multiply driven"?

Thanks in advance.

hi iVenky,

Multiply Driven is the condition when a single signal is been forced by multiple drivers or multiple inputs.
In case of code under consideration, generate will generate 8 statements out of the single statement written under it.
Because of which signal "accum" will be driven by a(0) to a(7) and b(0) to b(7).
Which is the cause behind the compiler error.
Remedy to this problem is make accum to be 2D array or work on the design.

for loops are unrolled - so therefore you've assign accum 8 times.

gck said:

hi iVenky,

Multiply Driven is the condition when a single signal is been forced by multiple drivers or multiple inputs.
In case of code under consideration, generate will generate 8 statements out of the single statement written under it.
Because of which signal "accum" will be driven by a(0) to a(7) and b(0) to b(7).
Which is the cause behind the compiler error.
Remedy to this problem is make accum to be 2D array or work on the design.

Click to expand...

Thanks but I don't find it to be logically wrong.Is that logically wrong?

This for Generate statements accum<="11111111" when (a(i) and b(i))='1' else "00000000";


unrolls
as

accum<="11111111" when (a(0) and b(0))='1' else "00000000";
accum<="11111111" when (a(1) and b(1))='1' else "00000000";
accum<="11111111" when (a(2) and b(2))='1' else "00000000";
accum<="11111111" when (a(3) and b(3))='1' else "00000000";
accum<="11111111" when (a(4) and b(4))='1' else "00000000";
accum<="11111111" when (a(5) and b(5))='1' else "00000000";
accum<="11111111" when (a(6) and b(6))='1' else "00000000";
accum<="11111111" when (a(7) and b(7))='1' else "00000000";


ie accum has 8 Drivers

---------- Post added at 16:19 ---------- Previous post was at 16:08 ----------

Another important fact >> VHDL For generate is meant for Structural replication ,

blooz said:

This for Generate statements accum<="11111111" when (a(i) and b(i))='1' else "00000000";


unrolls
as

accum<="11111111" when (a(0) and b(0))='1' else "00000000";
accum<="11111111" when (a(1) and b(1))='1' else "00000000";
accum<="11111111" when (a(2) and b(2))='1' else "00000000";
accum<="11111111" when (a(3) and b(3))='1' else "00000000";
accum<="11111111" when (a(4) and b(4))='1' else "00000000";
accum<="11111111" when (a(5) and b(5))='1' else "00000000";
accum<="11111111" when (a(6) and b(6))='1' else "00000000";
accum<="11111111" when (a(7) and b(7))='1' else "00000000";


ie accum has 8 Drivers

---------- Post added at 16:19 ---------- Previous post was at 16:08 ----------

Another important fact >> VHDL For generate is meant for Structural replication ,

Click to expand...

Thanks. I have a problem though. As I am new to VHDL I don't understand what you mean by the terms "Drivers" and "Structural replication".

You have to think of signals as wires on a circuit board. A driver is anything that is connected rather than leaving the wire open. If you have multiple things driving the same wire, you can get multiple driving errors.

Std_logic was meant to replicate the behaviour of real wires, hence why if you have two drivers for the same signal that oppose each other you get 'X'. But FPGAs forbid multiple drivers internally, hence why the code can compile and simulate with an 'X', but the synthesisor will throw a multiple driver error. Std_ulogic is more appropriate for FPGAs really as it only allows 1 driver, and wont even simulate with multiple drivers.

On to Generate - the Generate statement allows you to have conditional code (condition at elaboration time, not run time). It also allows you to replicate the same bit of code or entity instantiations many times:

for example: