Posting your code so others can see before I answer. Your code is as follows:
--create of multiplier 4bit X 3bit
library ieee;
use ieee.std_logic_1164.all;
--declaratio of the multiplier entity
entity multiplier4X3 is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (2 downto 0);
P : out std_logic_vector (6 downto 0)
);
end multiplier4X3;
architecture structure of multiplier4X3 is
--call of the 1Bit full adder
--component fulladder1 port(
--a,b,c: in std_logic;
--S,Co: out std_logic);
--end component;
--call of the 4Bit full adder
component fulladder4 port(
x: in std_logic_vector (3 downto 0);
y: in std_logic_vector (3 downto 0);
z: out std_logic_vector (3 downto 0);
Cout : out std_logic );
end component;
--call of the andgate component
component andgate
port (A,B: in std_logic;
D: out std_logic);
end component;
--set the middle signals to use for in-out
signal k,l,m,n,ztemp : std_logic_vector (3 downto 0);
signal Cout1: std_logic;
begin
--ztemp(3 downto 0) <= z (3 downto 0) ;
--the signals for the 12 AND gates
g1: andgate port map (A => A(0), B => B(0),D=> P(0));
g2: andgate port map (A => A(1), B => B(0),D => k(0));
g3: andgate port map (A => A(2), B => B(0),D => k(1));
g4: andgate port map (A => A(3), B => B(0),D => k(2));
g5: andgate port map (A => A(0), B => B(1),D => l(0));
g6: andgate port map (A => A(1), B => B(1),D => l(1));
g7: andgate port map (A => A(2), B => B(1),D => l(2));
g8: andgate port map (A => A(3), B => B(1),D => l(3));
g9: andgate port map (A => A(0), B => B(2),D => m(0));
g10: andgate port map (A => A(1),B => B(2),D => m(1));
g11: andgate port map (A => A(2), B => B(2),D => m(2));
g12: andgate port map (A => A(3), B => B(2),D => m(3));
--one of the middle signals must be set to GND
k(3)<='0';
--declaration for the procedure needed to use the two 4-bit full adder components
stage0: fulladder4 port map (x(3 downto 0)=>k(3 downto 0), y(3 downto 0)=> l(3 downto 0),ztemp(3 downto 0)=>(z(3 downto 1)=>n(3 downto 1), z(0)=>P(1)), Cout=>Cout1);
--stage1: fulladder4 port map (x(1)=>k(1), y(1)=> l(1),z(1)=> n(1));
--stage2: fulladder4 port map (x(2)=>k(2), y(2)=> l(2),z(2)=> n(2));
--stage3: fulladder4 port map (x(3)=>k(3), y(3)=> l(3),z(3)=> n(3),Cout=>Cout1);
--stage4: fulladder4 port map (x(0)=>n(1), y(0)=> m(0),z(0)=> P(2));
--stage5: fulladder4 port map (x(1)=>n(2), y(1)=> m(1),z(1)=> P(3));
--stage6: fulladder4 port map (x(2)=>n(3), y(2)=> m(2),z(2)=> P(4));
--stage7: fulladder4 port map (x(3)=>Cout1, y(3)=> m(3),z(3)=> P(5), Cout=>P(6));
--( 3 => n(3), 2 => n(2), 1 => n(1), 0 => P(1) )
end structure;
---------- Post added at 20:35 ---------- Previous post was at 20:32 ----------
The first problem I see is that the signal z used in this line:
--ztemp(3 downto 0) <= z (3 downto 0) ;
Is not declared anywhere. You must declare signals that are port mapped to your components. From the logic you are using it seems that you use the "n" signal as the z output from the full adders. So change the line to:
ztemp <= n; You don't actually eed the 3 downto 0 since both signals are of the same length and endianness.
Let me know if there are any other problems