Multiplication of float/real value in VHDL

[arunprasadvr3]

Hello,
I need to implement this exprestion in VHDL

Answer=((0.21*255)+(0.72*100)+(0.07*90))

Can anybody help me how to multiply the float values and roundoff the final answer

 

[KlausST]

Hi,

your whole expression is just a constant value: 131.85. No need to calculate anything in VHDL.

Klaus

 

[FvM]

VHDL can do the calculation for real variables or constants, need to convert the integer constants to real

e.g.

constant answer : real := (0.21*255.0)+(0.72*100.0)+(0.07*90.0);

or

constant answer : integer := to_integer(round((0.21*255.0)+(0.72*100.0)+(0.07*90.0)));

Real variables aren't synthesizable, depending on what you want to achieve, you'll refer to float or fixed point data type.

 

[arunprasadvr3]

Hi,
For understanding I have given constant value.

But the real expression is

Answer=((0.21*R)+(0.72*G)+(0.07*B))

R, G, and B are input for the module


Thanks,
Arun

 

[KlausST]

Hi,

now it´s a complete different situation.

Are you sure you need the output as "float"?
I´d avoid it.

Try to use integer or fixed point multiplication.

Klaus

 

[arunprasadvr3]

Hi,
I don't need output as float. I need the output as "integer"

Arun

 

[KlausST]

Hi,

integer...
Signed/unsigned? 8bit, 16 bit, 32 bit?

***

I´m no specialist in VHDL.
Thus here my "hardware style" explanation:

depending on what accuracy you need I recommend to replace it with integer multiplication.

Example:
0.21 x R

expand it by 2^16 = 65536

0.21 * 65536 * R / 65536

now combine:
(0.21 * 65536) * R / 65536

and make this an integer value (or let the compile do the job)
(0.21 x 65536) = 13763
--> 13773 * R / 65536

The hardware just calculates "13773 * R" (integer 16 bit x 16 bit multiplication)
and the "/65536" is just a shift 16 bits to the right. ... which indeed is replaced as "wiring" (it takes bits 0..15 of the result instead of bits 16..31)

Klaus

 

[niciki]

It looks like you want to convert RGB->grayscale.
You can do this without floating values at all.

---

Code VHDL - [expand]
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process(clk_pix)
begin
    if rising_edge(clk_pix) then
        grayPixel <= (x"4c"*redSignal + x"97"*greenSignal + x"1C"*blueSignal); --weighted color
    end if;
end process VideoEdition;
 
--output video signals
OUT_vid_data(23 downto 16) <= grayPixel(15 downto 8); --red channel
OUT_vid_data(15 downto 8) <= grayPixel(15 downto 8); --green channel
OUT_vid_data(7 downto 0) <= grayPixel(15 downto 8); --blue channel

---

The source:
https://miscircuitos.com/video-processing-fpga-zybo-using-vhdl/

 

[FvM]

For understanding I have given constant value.

But the real expression is

Answer=((0.21*R)+(0.72*G)+(0.07*B))

R, G, and B are input for the module

I think you are still learning to ask clear questions.

As far as I understand now, you want synthesizable VHDL. In- and output is 8 bit unsigned. The resolution of the fixed point factors need to be still defined, 8 bit could be a first guess. The code can be comfortably implemented using IEEE fixed point library or with elementary numeric_std operations. The latter similar to what KlausST suggested, converted to legal VHDL syntax.