Multiplication in Verilog with a constant

[Antares.]

I have to perform an action of division in my verilog code, I have to divide a 16 bit number by 10 and also take modulus of 10. But div and mod operations cannot be synthesized. Alternate option might be to multiply that number by a constant 0.1 instead of div. How can I do this? Also please suggest me an alternative to mod operation, which can be synthesized.