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multiplexer timing constraints

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vsheladiya

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hi,

i am using a mux in my design which is having two inputs: one is asynchronous input signal and other is clock. so can anyone tell me how should i give constraint to such design.

thanx in advace
vijay sheladiya
 

ljxpjpjljx

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you'd better have some protection mechanisim for this circuit!
 

vsheladiya

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thanx for reply...

which type of protection it requires?

regards,
vijay sheladiya
 

poor mystic

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Hi!
Give us a wee hint what's going on here! Is this to be sent over your own bearer or what?
But ordinarily you send your PCM stream on a pretty tight basis, with about as good attention to timing as is possible since relativistic effects are important here. PCM timing comes from atomic clocks.
Most modems used to synchronise to the bearer using a decent pll, when I studied this sort of work, and the data was conveniently loaded into a set of shift registers set up as a pipe in which words can be placed from the side. In the modern day I expect this would be carried out in a logic array.

(or did I miss the point?)
 

shitansh

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vsheladiya said:
hi,

i am using a mux in my design which is having two inputs: one is asynchronous input signal and other is clock. so can anyone tell me how should i give constraint to such design.

thanx in advace
vijay sheladiya

Hi,

What is select line of this mux, means is select line is asynchronous or it is in phase of clock (one input of mux)?

Constraint depends on that also.

HTH
Shitansh Vaghela
 

vsheladiya

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hi shitansh,

there is an asynchronous select line not a clock.

regards,
Vijay
 

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