I actually think most OS don't allow opening the same file multiple times. I've never seen anything like this done in VHDL or Verilog add I know for a fact that it doesn't work in Verilog (accidentally tried to open the same file twice because of a cut-n-paste error). Just try it out, but I don't think it will work.
That is likely because it keeps a local copy of the file in memory and only writes the file when it actually does a save, and not holding the file open all the time.
Your original question is something you could have found out much quicker if you'd have just set up a small example yourself.
Why not just open a file into an array then access the array in more than 1 place?