Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 if (expression1) reg1 = a+b; reg2 = reg2; reg3= reg3; reg4=reg4; reg5=reg5; ............... ............... else if ( expression2 ) reg1 = reg1; reg2 = c-d; reg3= reg3; reg4=reg4; reg5=reg5; ............... ............... ............... ...............
If you want to have the FlipFlop for those "registers", you Must use the non-blocking assignment.
You are using Blocking assignment which can be inferred to combinational logic or latch.
Having either reg2 = reg2 or omitting an assignment to reg2 in a combinational always block is both creating latches, which is probably unwanted.
To generate pure combinational logic, a default assignment for each variable should precede the conditional code.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 always (a.,b,c,d,e,....) reg1 = 10'b0; reg2 = 10'b1111011111; .................... .................... if (expression1) reg1 = a+b; reg2 = reg2; reg3= reg3; reg4=reg4; reg5=reg5; ............... ............... else if ( expression2 ) reg1 = reg1; reg2 = c-d; reg3= reg3; reg4=reg4; reg5=reg5; ...............
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module mname(m,ou); parameter n=6; parameter d=8; input [n-1 : 0] m; ouput [n-1 : 0] ou; reg [n-1 : 0] ou; reg [d-1,0]stor[n-1, 0]; integer i; reg [n-1, 0] s = 0,t= 2(n)-1; /* 2(n) means 2 to the power n */ always @(m) for (i=0, i<=(2(n-1))/2 , i=i+1) /* 2(n-1) means 2 to the power n-1 */ if (m < mem[(s+t)/2]) t= (s+n)/2 -1; else if ( m > mem[(s+t)/2]) s= (s+n)/2 +1; else ou = (s+n)/2 ; i=(2(n-1))/2; endmodule
The default variable assignment is the correct way to avoid unwanted latches in combinational codes.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 always (a.,b,c,d,e,....) reg1 = 10'b0; reg2 = 10'b1111011111; .................... .................... if (expression1) reg1 = a+b; reg2 = reg2; reg3= reg3; reg4=reg4; reg5=reg5; ............... ............... else if ( expression2 ) reg1 = reg1; reg2 = c-d; reg3= reg3; reg4=reg4; reg5=reg5; ...............
As for the search code, I'm not sure what you want to achieve. Is it an exercise using Verilog as a programming language or intended for hardware synthesis?.
In the latter case, do you really want a fully parallel implementation performing the search in one clock cycle?
Can you please describe how you will do that?Otherwise the search should be performed sequentially in clocked always block controlled by a state machine.
I have difficulties to read the code due to semantic errors (missing variable declarations and respective initializations).
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 module mname(m,ou); parameter n=8; parameter d=10; input [n-1 : 0] m; output [n-1 : 0] ou; reg [n-1 : 0] ou; reg [d-1,0]stor[n-1, 0]; integer i; reg [n-1, 0] s = 0; reg [n-1,0] t= 2n-1; always @(m) for (i=0, i<=2n-1 -1 , i=i+1) /* 2n means 2 to the power n. No superscript available to describe that. */ if (m < mem[(s+t)/2]) t= (s+n)/2 -1; else if ( m > mem[(s+t)/2]) s= (s+n)/2 +1; else ou = (s+n)/2 ; i=2n-1 -1; /* 2n means 2 to the power n. No superscript available to describe that. */ endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 always@(*) begin reg1 = init1; reg2 = init2; if (expression1) reg1 = a+b; else if ( expression2 ) reg2 = c-d; end
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 for (i=0, i<=2n-1 -1 , i=i+1) begin s=0; t=0; // necessary initial condition ou = OU_DEF; // to avoid latch generation if (m < mem[(s+t)/2]) t= (s+n)/2 -1; else if ( m > mem[(s+t)/2]) s= (s+n)/2 +1; else ou = (s+n)/2 ; end
Code Verilog - [expand] 1 2 for (i=0, i<=2n-1 -1 , i=i+1) /* 2n means 2 to the power n. No superscript available to describe that. */ if (m < mem[(s+t)/2])
Code Verilog - [expand] 1 2 3 4 5 6 7 8 // latch required in always @(*) blocks wire IN_sig; reg RHS_sig, LHS_sig // This is a latch as LHS_sig appears on the right hand side of the assignment. // i.e. if RHS_sig is low latch is transparent, if RHS_sig is high LHS_sig is latched. always @(*) LHS_sig = LHS_sig & RHS_sig || IN_sig & ~RHS_sig; end
You'll also omit the useless identity assignments
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 always@(*) begin reg1 = init1; reg2 = init2; if (expression1) reg1 = a+b; else if ( expression2 ) reg2 = c-d; end
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 reg reg1 = init1; reg reg2 = init2; always@(*) begin if (expression1) reg1 = a+b; else if ( expression2 ) reg2 = c-d; end
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 for (i=0, i<=2n-1 -1 , i=i+1) begin s=0; t=0; // necessary initial condition ou = OU_DEF; // to avoid latch generation if (m < mem[(s+t)/2]) t= (s+n)/2 -1; else if ( m > mem[(s+t)/2]) s= (s+n)/2 +1; else ou = (s+n)/2 ; end
Otherwise design a clocked always that performs one iteration step per clock cycle.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 if (m < mem[(s+t)/2]) t= (s+t)/2 -1; else if ( m > mem[(s+t)/2]) s= (s+t)/2 +1; else ou = (s+t)/2 ;
reg reg1 = init1;
reg reg1;
initial reg1 = init1;
Can a RTL for a FSM have internal reg vectors which are neither outputs of the FSM nor the reg variables for the present state and next state of the FSM? For example if we can declare a reg vector for a if-else iteration in Verilog like below in the next state logic of FSM for s and t ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 if (m < mem[(s+t)/2]) t= (s+t)/2 -1; else if ( m > mem[(s+t)/2]) s= (s+t)/2 +1; else ou = (s+t)/2 ;
Why not read the verilog language reference or simply trying if your compiler accepts it?Code:reg reg1 = init1;
The "variable declaration assignment" is the equivalent of a declaration plus initial statement.
It's only executed once and thus not suitable for preventing latch generation in combinational always block.Code:reg reg1; initial reg1 = init1;
for (i=0, i<=2n-1 -1 , i=i+1)
begin
if (m < mem[(s+t)/2])
t= (s+n)/2 -1;
else if ( m > mem[(s+t)/2])
s= (s+n)/2 +1;
else
ou = (s+n)/2 ;
end
Can a RTL for a FSM have internal reg vectors which are neither outputs of the FSM nor the reg variables for the present state and next state of the FSM? For example if we can declare a reg vector for a if-else iteration in Verilog like below in the next state logic of FSM for s and t?
The variables have to be declared somewhere, which has been omitted in my code example snippet. It's not the point where the variables are declared. If the variable value is kept between iterations, combinational code synthesis may become difficult or even impossible, as mentioned by ads-ee.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test ( input [3:0] in, output [3:0] ou ); reg [3:0] s = 0; integer n; always @(*) begin for (n=0;n<3;n=n+1) begin : gen_s s = s + 1; end end assign ou = s + in; endmodule
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