omara007
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Hi Guys
I want to design my register file so as to have 5 simultaneous synchronous write ports. I have one concern regarding how to make the design capable of handling the situation, if by mistake, 2 write addresses are the same. Given that my register file is simply a 2 dimensional array of std_logic ..
here is the type:
I want to design my register file so as to have 5 simultaneous synchronous write ports. I have one concern regarding how to make the design capable of handling the situation, if by mistake, 2 write addresses are the same. Given that my register file is simply a 2 dimensional array of std_logic ..
here is the type:
Code:
type regfile_type is array (0 to (2**(addrs_width))-1) of signed (data_width-1 downto 0);