Multiple Grounds issues in Cadence LVS

[Ali263]

Hi ,

I am designing a circuit in 65nm cmos process which has different VSS connections for analog and digital part(VSS! and AVSS).

However whatever i do, i get the below 50, 50 errors as shown in picture attached.

Can someone understand from the attachment what exactly it means?
What is the meaning of two **VSS! or **AVSS?

 

[timof]

It's clear what it means - you have one net, AVSS, in the schematic (source), but two nets in the layout - AVSS and VSS!

Somehow, the bulk of the MOSFETs gets connected to VSS! - that why there is instance (pin) mismatch between schematic and layout.

I do not know how to resolve this, but this should be a pretty standard situation, and the resolution should be easy and well known.

You can try declaring AVSS net as a ground - the instance mismatches should go away (but net mismatch will still be there).

 

[dick_freebird]

Many PDKs have inherited connections that default to a "safe" global net like vss! If the net property is not set explicitly or by wire with the B terminal exposed. Check properties for stale VDD! references.