Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Multiple FPGA devices

Status
Not open for further replies.

jdhar

Full Member level 5
Joined
Aug 16, 2004
Messages
258
Helped
16
Reputation
32
Reaction score
2
Trophy points
1,298
Activity points
2,753
Hi,

I wish to build a JTAG interface for my FPGA projects. Currently, I have the 25 pin parallel port cable going to a header on my board with an FPGA on it, and then level converting circuitry to shift it down to 3.3V from 5V. However, the problem with this is that 1) Extra circuitry required on the board just for JTAG connection, and 2) I can only use one board at a time. So, I would like to build another board that takes the 25-pin parport cable in one end, and then 2 or 3 smaller headers (5x2) that can connect to multiple boards. these headers need to supply 2 sets of signals - one 'hard' JTAG that connects to the JTAG signals on the FPGA, and one 'soft' JTAG set that connects to user-defined signals on the FPGA. The soft JTAG chain is used for Nexus 5001 communication to any processors etc.. on the FPGA's.

How would I go about doing this? Anyone who has any knowledge of Protel's nanoboard or LiveDesign evaluation board should be able to help here. Can I just connect the TDO of one header to the TDI of the next and so on?? will this work for the soft JTAG chain also?

Thank you, Jai.
 

Hi, I only have experience with CPLD's, and I have successfully chained them for download. As you said, from the 'dongle's TDI to the FPGA's TDI, then the FPGA's TDO to the next FPGA's TDI etc.. The rest of the connections (TCK, TMS, PWR, GND) are all in parallel.

But this is for CPLD's, an FPGA uses an on-board memory, to hold the downloaded design, and then load it into the FPGA on power-up. I guess that doesn't really matter, you just JTAG your design into these chips instaed, or the FPGA itself for temp operation (I could be wrong, I have no experience with FPGA's).

Btw, what FPGA's are you using? Xilinx, Altera, Lattice??

Anyway, you mentioned 'level shifting' on your boards, or is it in the 'dongle' (download cable)?? Because you could easily have 3,4 or more ribbon cables coming out of the dongle, one for each board, and these go direct to the FPGA/memory, if your lelvel shifting, or buffer circuitry is inside the dongle. And as I sid above, the wiring would be simple since 4 of the wires are the same connection, and the TDI,TDO just loops. But make sure you label the ribbon cables their place in the chain (1,2,3 etc).

As I said, I'm no expert,

BuriedCode.
 

The level shifting will be on the board that I'm designing - I don't wish to have fly leads on the ribbon cables since that's just messy, which is why Im' making a board that does the level shifting and jTAG chaining. I guess I'm more concerned about how Protel will work with this chain.

Added after 18 seconds:

oh, and I'm using Altera's Cyclone
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top