multiple driver can drive one signal

[yburake]

hi,
i have two clocks in 32mhz but one of them is delayed 10ns. i need a 10ns pulse width 32 mhz signal so i have to use both delayed signal rising_edge and normal signal rising_edge.
but i have problems about synthesis. can i control the output signal with these two clocks without synthesis problem.

Thanks in advance,
Burak

 

[TrickyDicky]

That sounds like a recipe for disaster. First you can only use 1 clock in a process, and secondly you can only drive a signal from 1 process

What you need is one of two options:
1. A double register to get data across the clock domain boundry
2. Stick a FIFO between the clock domains. Both Altera and XILINX provide FIFO IP blocks.

 

[yburake]

I need a flip flop that reacts on the edges of two different signals. I need this to be synthesizable

if(rising_edge(sig1)) then
bit <= '0';
elsif(rising_edge(sig2)) then
bit <= '1';
end if;

 

[TrickyDicky]

Then you'll be out of luck - your code is impossible in all FPGAs.

 

[yburake]

i know the code is impossible,but i asked maybe there are tricks or manupulations to do same job.

 

[FvM]

Assuming, the clock timing is clearly defined, then the timing analysis of FPGA synthesis tools will be able to deal with the two clocks and generate logic without timing violations. The most easy way to get a 10 ns pulse is to AND both clock signals, also FF outputs from both clock domains can be combined to form the intended waveform.

 

[mrflibble]

The most easy way to get a 10 ns pulse is to AND both clock signals, also FF outputs from both clock domains can be combined to form the intended waveform.

Agreed. That's how I'd do it as well.

You have 1 flipflop for each clock domain. Toggle them at the posedge of their respective clock. So the flipflops are both regular boring synchronous design, and they get clocked 10 ns distant from each other.


And then you combine the 2 flipflop outputs using some combinatorial logic. AND, XOR, something like that, and you have your 10 ns pulse.

 

[yburake]

thanks for all your advice, they were very usefull.

 

[Mahrous]

if you are using xilinx tools you may look at the " ODDR2" HDL macro ,
it has 1 output , 2 inputs , 2 clocks
output is changed on both edges , on clk1 rise in1 is the output , on clk2 rise , in2 is the output

and i think you may write your code using multiplexers

 

[mrflibble]

I need to read documentation more carefully.

 

[FvM]

you may look at the " ODDR2" HDL macro

DDR output registers, as available with most newer FPGA families, are a combination of registers and an output multiplexer. If the inputs are constant, using ODDR2 means nothing but using a multiplexer for the output. A DDR output register would be helpful, if the inputs are changing, e.g. to generate a single pulse or a variable pulse sequence. But it can be applied to output signals only.

 

[mrflibble]

... A DDR output register would be helpful, if the inputs are changing, e.g. to generate a single pulse or a variable pulse sequence. But it can be applied to output signals only.

If I recall correctly, at least for a spartan-6 you could use the DDR output for internal use. The side effect is that the associated IOB can no longer be used as an output,. The output of the DDR2 is routed to the fpga fabric instead.

I'll see if I can find that reference about that...