yburake
Newbie level 4

hi,
i have two clocks in 32mhz but one of them is delayed 10ns. i need a 10ns pulse width 32 mhz signal so i have to use both delayed signal rising_edge and normal signal rising_edge.
but i have problems about synthesis. can i control the output signal with these two clocks without synthesis problem.
Thanks in advance,
Burak
i have two clocks in 32mhz but one of them is delayed 10ns. i need a 10ns pulse width 32 mhz signal so i have to use both delayed signal rising_edge and normal signal rising_edge.
but i have problems about synthesis. can i control the output signal with these two clocks without synthesis problem.
Thanks in advance,
Burak