[SOLVED] multiple assignments in verilog

[gnoble29]

I have written the following verilog codes.....The first one will execute in one clock cycle......But due to multiple assignments of variable ,the second code is not executing in one clock cycle.....Can anyone suggest any method so that the second code also will execute fully in one clock cycle????
PLZ HELP


//pgrm 1

always @(posedge clk)
begin

s<=8'h01;
s_rot <= 8'h01;
s_2<= 8'h03;
s_out1<= 8'h01;
s_out2<=8'h01;

end


//pgrm 2

always @(posedge clk)
begin

s<=(DATA_WIDTH-m);
s_rot <= s<<1;
s_2<=s+8'h03;
s_out1<=s_rot+8'h01;
s_out2<=s_rot+s_2;

end

 

[TrickyDicky]

What you have in the second always block is a chain of registers. So each stage completed in a single clock cycle, and the pipeline length is 5.

To complete the lot in a single pipeline state, you need to use non-blocking assignments with the = rather than <=.

But, even though it may complete in a single clock cycle, the max clock speed will be lower. So even though the latency is lower with non-blocking, as the code you already have can be clocked higher the throughput may be higher with the higher latency. (and it may be significantly higher, like 2 or 3x or more).

 

[gnoble29]

thankyou sir...I changed <= to =....Now its working in single clock..