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Multidriven Signals due to for loop in verilog

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hassanzia

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Hi all,

if A,B and C are 8 bit deep RAMS then why does this code produces a multidriven signal error

Code:
for (i=0;i<16;i=i+1)
begin
  for (j=0;j<8;j=j+1)
    begin
      A[i][j] = B[i][j] ^ C[i][j];
    end
end

whereas this one produces no error
Code:
for (i=0; i<16; i=i+1)
begin
  A[i] = B[i] ^ C[i];
end
 

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