Multicycle Hold analysis

Status
Not open for further replies.
K

kumar_eee

Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
113
Trophy points
1,323
Location
Bangalore,India
Activity points
4,677
Can anyone tell me about multicycle hold analysis? Does it affect the frequency of the chip?
 

Hi Kumar,

By default hold check is done once clock edge prior to the setup check. So same holds for Multi cycle path..If u want the check to be performed on the same edge as the launch we need to specify to the tool using a command...

cheers
 

multi cycle hold is done by specifications of the designer when you are sure that the path takes more than 1 cycle.You can specify the edge for setup and hold checks
 

And speaking about frequency...Multi cycle path is specified when your logic is working slower than the base clock frequency............correct me if I'm wrong
 

agree what the said of jeevan.life.

====
Multi cycle path is specified when your logic is working slower than the base clock frequency............correct me if I'm wrong
====

we do MCP analsysi for setup time, hold will change due to setup edge change.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…