Multi Supply and Multi VDD for Low Power Design

[hb_cancer]

multi vdd

Hi,

Can your please point out the actual differences between Multi Supply and Multi VDD in low power ASIC design. On what scenario is the decision made to follow any one of the Power Scheme.

Thanks...

 

[vlsichipdesigner]

on chip regulator mvdd low power voltage islands

hi,

my 2 cents,

i believe when you say multi supply , you mean voltage scaling or so,
voltage regulator , varies the voltages according to the system requirement and the control of the power controller say you chip has both voice and data, now when the user is using data portion of the chip the voice portion cannot perform at full speed , so a signal can be activated and the voice portion voltages can be reduced and there by power can be saved.

multi VDD means , you partition the chip accordingly , say one portion of the chip with high VDD and another portion with low VDD means one which is timing critical and which is at full speed you can design with high VDD similar with less critical can be with low VDD this is called "voltage islands", based designs and you place level shifters in better to ensure proper data transfers across if there is any.

you can have both the options in a chip or a design it is purely design dependant and the architecture of your design and how critical power is a constrain in your chip.

myprayers,
chip design made easy
https://www.vlsichipdesign.com

 

[hb_cancer]

multi vdd design

Hi vlsichipdesigner,
Thanks for your response! but I have a query, when you say "place level shifters"can you please elaborate on it and also on " in better to ensure proper data transfers across " Thanks !

 

[raki31]

multi vdd design

multi VDD means same supply but v r increasing no. of rails....

where as multi supply means if our design has cells with different voltage requirments
...........

 

[AdvaRes]

low power header cell

multi VDD means same supply but v r increasing no. of rails...............

Coud you please explain ?

 

[raki31]

multi supply

hey forget my post....

i haven't seen vlsichipdesigner post at the top, he gave detailed description... plz refer that ok......thanku.....

 

[hiral.kotak]

low power design methodologies retention cell

Hi,

Multivoltage cells can be used in multi voltage design (Mvdd) in which there are different voltage domains. for e.g.
Special cells are required for implementing a Multi-Voltage design.

1. Level Shifter
2. Isolation Cell
3. Enable Level Shifter
4. Retention Flops
5. Always ON cells
6. Power Gating Switches/MTCMOS switch

Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS's are very simple whereas L2H LS's are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale.

Isolation Cell: These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an 'always on' region only and the enable signal of the isolation cell needs to be 'always_on'. In a nut-shell, an isolation cell is necessary to isolate floating inputs.
There are 2 types of isolation cells (a) Retain "0″ (b) Retain "1″

Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.

Retention Flops: These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down. All the paths leading to this register need to be 'always_on' and hence special care must be taken to synthesize/place/route them. In a nut-shell, "When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used".

The retention flop has the same structure as a standard master-slave flop. However, the retention flop has a balloon latch that is connected to true-Vdd. With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch. Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.

Always ON cells: Generally these are buffers, that remain always powered irrespective of where they are placed. They can be either special cells or regular buffers. If special cells are used, they have thier own secondary power supply and hence can be placed any where in the design. Using regular buffers as Always ON cells restricts the placement of these cells in a specific region.

In a nut-shell, "If data needs to be routed through or from sleep blocks to active blocks and If the routing distance is excessively long or the driving load is excessively large, then buffers might be needed to drive the nets. In these cases, the always-on buffers can be used."

Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-threshold CMOS, where low-Vt gates are used for speed, and high-Vt gates are used for low leakage. By using high-Vt transistors as header switches, blocks of cells can be switched off to sleep-mode, such that leakage power is greatly reduced. MTCMOS switches can be implemented in various different ways. First, they can be implemented as PMOS (header) or NMOS (footer) switches. Secondly, their granularity can be implemented on a cell-level (fine-grain) or on a block-level (coarse-grain). That is, the switches can be either built into every standard cell, or they can be used to switch off a large design block of standard cells.

Hope this will help you.

Thanks.

HAK.

 

[raki31]

site:www.edaboard.com low power

hi,

my 2 cents,

i believe when you say multi supply , you mean voltage scaling or so,
voltage regulator , varies the voltages according to the system requirement and the control of the power controller say you chip has both voice and data, now when the user is using data portion of the chip the voice portion cannot perform at full speed , so a signal can be activated and the voice portion voltages can be reduced and there by power can be saved.

multi VDD means , you partition the chip accordingly , say one portion of the chip with high VDD and another portion with low VDD means one which is timing critical and which is at full speed you can design with high VDD similar with less critical can be with low VDD this is called "voltage islands", based designs and you place level shifters in better to ensure proper data transfers across if there is any.

you can have both the options in a chip or a design it is purely design dependant and the architecture of your design and how critical power is a constrain in your chip.

myprayers,
chip design made easy
https://www.vlsichipdesign.com

can u plz elaborate about voltage islands.....! thanku