Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Multi stage ICG

jeevan.life

Full Member level 5
Joined
Jun 26, 2010
Messages
241
Helped
83
Reputation
164
Reaction score
77
Trophy points
1,308
Location
Bangalore
Activity points
2,444
Why do I need multi stage clock gating? I can insert a root ICG at clock source and that should cut off my clock. What is the need to have downstream clock gates ?
 

oratie

Full Member level 6
Joined
Jan 10, 2007
Messages
348
Helped
176
Reputation
350
Reaction score
170
Trophy points
1,323
Activity points
3,701
Root ICG cut off clock for the whole design. But, you can want to cut off clock just for part of design. During the real operation of your design some flops may not switching, so it is reasonable to stop clock propagation to these flops.
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,181
Helped
382
Reputation
764
Reaction score
396
Trophy points
83
Activity points
11,147
Why do I need multi stage clock gating? I can insert a root ICG at clock source and that should cut off my clock. What is the need to have downstream clock gates ?
synthesize any relatively complex RTL with automatic clock gating on. You will see the tools will infer many enable conditions for different flip-flops. A single clock gating cell would not be enough to achieve this functionality.
 

Qwerty112233

Newbie
Joined
May 21, 2021
Messages
4
Helped
1
Reputation
2
Reaction score
0
Trophy points
1
Activity points
65
Simple analogy is power controls in a house. It's better and more practical to have power switches for every room in your house too.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top