module top (clk, out_slow, out_fast);
input clk;
wire clk_slow, clk_fast;
output out_slow, out_fast;
BUFG buf1 (.I(clk), .O(clk_slow));
BUFG buf2 (.I(clk), .O(clk_fast));
core_slow core1 (.clk(clk_slow), .out(out_slow));
core_fast core2 (.clk(clk_fast), .out(out_fast));
endmodule
module core_slow (clk, out);
input clk; // synthesis attribute PERIOD clk "70 MHz";
reg [79:0] count = 0;
output reg out = 0;
always @ (posedge clk) begin
count <= count + 1;
out <= ^count;
end
endmodule
module core_fast (clk, out);
input clk; // synthesis attribute PERIOD clk "150 MHz";
reg [31:0] count = 0;
output reg out = 0;
always @ (posedge clk) begin
count <= count + 1;
out <= ^count;
end
endmodule