[SOLVED] multi-clock problem - how to avoid timing violations

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Multi-Clock Problem

In our design, we have to use multiple clocks with different frequency. But these clocks are generated from one clock source.
Technically, this is not multi-clock-domain problem. So inter-block signals are not that hard to design.

But in the back-end flow, we encountered lots of timing violations on these inter-block signals. According to the reports, the clock tree is biggest problem. We have to modify our design.

What do you guys think that we should be careful in the next version? Or is there anything we can do in the back-end flow to avoid timing violations?

Thank you.

 

[FvM]

Multi-Clock Problem

The problem is most likely in the way, how you generate the clocks. Assuming, all derived clocks are generated by synchronous registered logic from the clock source. Then they have no timing difference in between, but are delayed related to the clock source. Thus a path from clock source to derived clock domain has problems. The problems may be much worse, if additional logic is involved after clock divider registers or ripple clock dividers are used.

 

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Re: Multi-Clock Problem

Thank you FvM.

Yeah, the delay is what we really concerned about now.
I'm sorry that I forgot to say we will insert clock gating cells in the tree. and to achieve as low power and area consumption as possible, we attempt to insert them manually to the root of clock tree.
But the large delay of clock tree (because of balancing different generated clocks) causes lots of timing violation, if we do so.

I think this is the trade-off point: overhead of clock gating insertion vs. timing violation. Currently, it seems if we want to avoid timing violations, we have to insert many clock gating cells far away from the the root of clock tree. That's terrible.

Is this the truth?

 

[kbulusu]

Re: Multi-Clock Problem

cant you create a separate clock tree for each of these generated clock tree sinks and then balance these 2 sub trees..what is the latency you are seeing? how close are the gators to the sinks? how is your enable pin timing ? Do you set -ve latency constraints on these enable pins of the clock gator? if you can provide more information, we can see what might be needed ...

 

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Re: Multi-Clock Problem

Thank you kbulusu.

I have to say we haven't gone that far in our next version. I think you are right. We need more information to determine the real problems. I just want to reduce the risk beforehand.

 

[AdvaRes]

Re: Multi-Clock Problem

Hi,

Actually you have to decide first how to look at the problem.
Since the different clocks are generated from the same global clock the different clocks frequency are the same but their phase are differents. This difference in phase is constant. So your circuit is no longer seen as a synchronous system but as a mesochronous system. In a mesochronous system delays and skews in the data and clock path results in the phase difference. Many solution can be used but this depend on the requirement and the resources.
The best way is to use the technique of buffer insertion for the equilibration. This solution is efficient but very sentitive to PVT variation. Other solutions use PLL/DLL for synchronization between the different frequency Ilands.

I suggest you to go for the mesochronous interconnect solution. This solution seems to be effiective but since it is a new axe of research you will not find good documentation in the WWW.


Hope it helped.
Cheers,
Advares.

 

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Re: Multi-Clock Problem

Thank you Advares.

I think the solution with PLL/DLL is far too complicated for our design (about 10k gates). But I will keep the mesochronous solution in mind.