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MSP430 pin shorted to GND when off

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shredder929

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I've got an odd problem here. I have this board with an MSP430F5435, and pins 39 and 40 are being used for UART communication, going to a port used for configuration through a PC app. The port is 4 pins, Rx, Tx, GND, Vcc. Pin 40 is the Rx line, pulled up to Vcc by a 100k resistor. Pin 39 is Tx and goes straight to the config port, no external pulllup/pulldown.

Normally when the device is off, pin 39 is just open, and then when powered on, the MSP internally pulls it to GND and then goes up and down as needed to transmit. But I have a couple devices here that can't communicate over UART because pin 39 is hard shorted to GND internally to the MSP. Even when the board is powered off, the Tx line is shorted to GND. I pulled the pad off the board, even pulled the pin off the body, and found the body contact for the Tx line is shorted to GND, so it's definitely an issue in the MSP itself. Because it's shorted, the MSP can never assert high and cannot transmit. We have found that they can receive though. If I send a reboot command from my PC app, it reboots, the MSP is running its code fine otherwise, we just don't get any feedback.

These units were tested and working fine when they left, some got this problem after being in the field for a year, but I have one that got this problem when it got to the customer. The cable is just a USB serial cable, FTDI driver, nothing special. Plugging it in backwards or offset and stuff doesn't seem to break anything. We don't think its ESD either.

Have any of you seen this issue before, where an MSP pin is inexplicably shorted to GND internally even when off?
 

It sure SOUNDS like it could be an ESD-related problem. Why DON'T you think it's ESD? Or, could it be an over-voltage? What happens if there's voltage on that pin, but the MSP is not powered?; that can cause problems. ICs don't spontaneously develop internal shorts. Is the pin routed directly to the connector and then the outside world? I'm not a big fan of that.
 

I feel like if it were an ESD issue, we would see it happen more often here at the office, and see it with more than just that specific pin. I configure devices hundreds of times throughout testing, often walking around a carpeted office, plugging and unplugging the cable over and over. Sometimes I plug it in the wrong way or off by one, I've never seen an issue and nobody else here has either.

There isn't really a way for the user to put any voltage on the header. We use the same MCU across multiple devices, some of them have sensor I/O that a user could potentially accidentally touch to the header, but this problem is also happening on a device where there's no sensor, it's fully encapsulated, and the only way the user can interact with the device is the configuration port.

The pin is directly connected to the configuration header pin yes.

Also for reference, this has happened on only a handful of devices over the years out of tens of thousands of units. There may be many more but these devices are generally configured once or twice and then installed and left there for a while, and rarely reconfigured for their life. They can also be configured wirelessly over the air which is what a lot of people do, so it's quite possible there's many more out there with this issue that we don't know about, so the numbers on how big of a problem this is are fudged.
 

Have you talked to the manufacturer? Since you've apparently bought tens of thousands of units, you're probably a good customer. They might take a bad device and do an autopsy on it for you; maybe identify a root cause.

Years ago, I had a flip-flop that kept exhibiting weird timing behavior. But not all of them. I got the mfr involved and they found that the problem was related to devices only from a particular fab.
 

When Vdd drops below 1.8V all bets are off as to what the GPIO pin is doing. Thats true
of pretty much all processors, when internal supply no longer high enough to meet
thresholds no telling what the output pin is going to do. In good datasheets there is
a Vcc/Vdd operating region for which specs are meet and logic functions. The 430 datasheet
I looked at was missing that, unfortunately.

You are trying to rely on NMOS Mosfet internally to ground being off, high Z, although it could have some
gate charge that has to leak off in order to force it off, to high Z essentially.


Regards, Dana.
 

Hi,
got this problem after being in the field for a year,
Sounds like a typical ESD problem.
Do you have some ESD protection on this pin?

Is the pin connected to anything outside the PCB during start up procedure?

Klaus
 

Hi,

Sounds like a typical ESD problem.
Do you have some ESD protection on this pin?

Is the pin connected to anything outside the PCB during start up procedure?

Klaus

There's no ESD protection on the board for that line. The pin is connected straight to one of these headers and nothing else: https://www.digikey.com/en/products...6-4/109006?s=N4IgTCBcDaIIIEYCcYwFoByAREBdAvkA

Is it recommended to put a 10k series resistor in line with the Tx pin, or would that make it harder to drive?
 

Hi,

Show your schematic. And describe which pins are used for what.

Show photos of your (connected) application.

The shown connector surely is no problem, maybe there is/was something connected to it. If so: what?
Do you have an ESD protected area in all your production and stock?
What power supplies do you use?

Klaus
 

Relevant part is attached, can't post the full schematic. The cable used to connect with the port is one of these, but with a different mating connector for the header I linked earlier up. As far as layout goes, there's no vias nearby, and the trace doesn't run within even 20mils of another line.

The production and shipping area is ESD protected, yes.

1617836338391.png
 

Hi,

A good reliable design includes an ESD protection at each signal that enters/leaves the PCB.

The piece of circuit just shows there is no protection.
But "no protection" does not mean this is the problem. What really causes the problem is else where. Not shown.

So if you need help ... you need to show us.

Klaus
 

Ah sorry didn't properly link it. The cable used to configure the device is this but with a different mating connector: https://ftdichip.com/products/ttl-232r-3v3/

That's about it, there's nothing else to show. It's a GPIO pin used for UART Tx connected to a header that sometimes might be plugged in with the linked cable. Plugging in the cable backwards or offset does nothing. Users aren't typically directly touching the header, they're just plugging the cable in.
 

Hi
there's nothing else to show.
ESD means electrostatic discharge.
ESD is not caused by the snippet of schematic you show.
ESD is not caused by the connector and not by the cable.

But all these things show the (possible) way of the ESD current.
But still it's not complete. Still informations are missing .. I'm not able to help.

Klaus
 

Plugging in the cable backwards or offset does nothing.
So far it's the result of single tests, but is fail safe behaviour guranteed by design? We don't know which TTL 232R pins may be connected to configuration connector in case of wrong insertion. Also, where's the 3.3V signal connecting to? Do you supply your board through TTL232R 3.3V output?

I also agree with the comments regarding ESD strength. I would consider a staggered protection: connector - TVS-diode array - series resistor - CPU
 

This ESD case certainly suspicious. But if I read your post correctly you depend on
an unpowered CMOS pin to have a specific state, to be off. I don't think that is viable.

For starters if the Vdd supply is disconnected you could drive the MSP430 power
rail inadvertently thru its GPIO pin parasitic diode. Even possibly power it up past BOR
threshold point. Noise, spikes, data on that pin from external source. And this would not
have consistent results across parts because of wide variation in circuit thresholds and other
factors.



1617998816643.png


If the Vcc pin has a path to ground situation still unreliable because of these parasitics and
their ranging values of threshold.


If you look at datasheet pin state is clearly defined by a range of Vdd, which when chip operated with no supply
is not defined in the datasheet. And even though you have rarely seen this there is a boatload of experience
by semiconductor guys on part to part inconsistent gremlins randomly showing up in some designs. Everything
from logic to linear.

Just a thought.

As a last resort consult TI directly on this, they would know.

Lastly when the 430 powers up I would not be surprised to see crap on a pin before it hits BOR, and issue
to contend with on the "normal" turn on side of operation.


Regards, Dana.
 

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