Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[moved] VLSI Layout using electric

Status
Not open for further replies.

Dahlia94

Newbie level 3
Joined
Dec 25, 2016
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
20
I have an ERC error: No N-Well contact in this area
it points to the error area which I try to connect pMOS to nWell ''nwell I used it as Export to make VDD''
can anyone help me ?!
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top