Both of these are simple VHDL constructs, which can be found on any VHDL tutorial site. You should probably visit one of those sites to learn some VHDL before tackling this project.
- - - Updated - - -
Ugh, gated clocks, you should not use gated clocks in an FPGA you'll probably never get the design to work reliably. Make a synchronous design using a single higher speed clock instead of generating a bunch of "clocks" from random signals. You will have more success with the implementation tools for FPGAs if you make a synchronous design.
If you can't translate from the blocks in your block diagram to the actual circuits that are required then I see no point in helping further as what you really need help with is learning basic digital design.